Paddle counter

Now for the counter\register block.

Even bits: low_active carry input, high_active carry output, bit is stored in non_inverted form.

Odd bits: high_active carry input, low_active carry output, bit is stored in inverted form.

The signal I had labeled 'PDET' is wired together for counter bit 7..0, with a pullup to +5V. It is 1, when the counter is $FF.

if one or more of the counter bits 7..0 is 0, PDET is tied to GND.

The layout of the paddle counter looks completely different from the layout of the envelope DAC counter, but from the logic level design point of view, the concept for both counters seems to be a little bit similar.