Oscillator

The Oscillator is a 24-bit phase-accumulating register which is incremented at each cycle by adding a 16-bit programmable value that controls the pitch.

Here is one of the bits, the Frequency register on the right and a ripple-carry adder on the left. Even bits have inverted logic to save some silicon and speed up the carry chain.

The freq register bits are formed by a couple of inverters where the feedback loop is clocked by sid_clk1. The input is taken from the data bus for the lower 16 bits while upper 8 bits are grounded. The input is enabled by the $0 line (FREQLO) for the low eight bits and $1 (FREQHI) for the others.

Then there is a ripple-carry adder which performs the summing of the oscillator value and the freq register.

This is the circuit that calculates the inverted sum:

And this one calculates the inverted carry:

resulting in the following expressions:

• /S = ¬((osc_x ∧ freq_x ∧ Cin) ∨ (/Cout ∧ (osc_x ∨ freq_x ∨ Cin))
• /Cout = ¬((osc_x ∧ freq_x) ∨ (Cin ∧ (osc_x ∨ freq_x)))

The resulting sum is latched (inverted for odd bits) at sid_clk2 and then NORed with the osc_rst signal at sid_clk1 producing the output. So when osc_rst is high the oscillator is reset to zero. The output is sent back to the adder, after passing through an inverter for odd bits. The output of the upper 12 bits is then used for the actual waveform generation.

The osc_rst line is controlled by the following circuit:

giving the following expression:

• osc_rst = ¬(¬test ∧ (¬sync ∨ ¬V3 ∨ V3_prev)) = test ∨ (sync ∧ V3 ∧ ¬V3_prev)

where V3 is the MSB of the preceeding voice generator and V3_prev is the value of V3 during the previous clock cycle. This means that the oscillator is reset when test bit is set or when sync bit is set and the sync source voice's MSB switches from low to high.