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ADSR registers
The ADSR registers bit:
Just two inverters with a clocked feedback loop:
The A, D and R values are gated so they are active only during the specific envelope phase:
The gates are controlled by the Gate bit and the R0 signal (counting direction):
So we have:
- atk_gate = R0
- dec_gate = ¬(rel_gate ∨ R0) = ¬R0 ∧ Gate
- rel_gate = ¬(R0 ∨ Gate) = ¬R0 ∧ ¬Gate
One funny fact is that in the first cycle of the attack and decay phases the wrong rate is used, as the R0 line reacts with one cycle delay.
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Wave Selector
Envelope Overview
Envelope Counter
Sustain Comparator
ADSR registers
Counter Logic
Exponential Divider
LFSR15 counter
LFSR5 counter
Analog stage overview
6581 DACs
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8580 DACs
8580 Virtual ground
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