Exponential Divider

The inverted and non-inverted outputs of the envelope DAC counter are feeding 7 AND gates that check for the following values, at which the decay rate is changed: $00, $06, $0E, $1A, $36, $5D, $FF.

The outputs of two of those AND gates goes to the envelope\counter control circuitry, detecting if the counter is $00 or $ff.

But those 7 AND gates also feed five RS flipflops through transparent latches (transparent during sid_clk1).

Circuitry for one of those five RS flipflops:

During 'Decay phase' and 'Release phase', the outputs of those five RS flipflops which are feeding the small PLA above the LSR5 counter cause a non-linear decrease of the envelope DAC counter value by slowing down the DAC counter... according to the value the DAC counter has at the outputs.

In my big block diagram, I had simplified things by drawing just one transparent register between the RS flipflop outputs and the small PLA instead of 15 tiny registers, sorry. :)

The FPF output of those five RS flipflops is wired together with a pullup to +5V, so if all five RS flipflops are cleared, FPF isn't tied to GND and thus '1', which makes the envelope DAC counter run at a normal (not slowed down) speed during 'Decay phase' and 'Release phase'.

BTW: not more than one of those five RS flipflops is supposed to be set.