POT registers

Nothing fancy about the registers for POT_X, POT_Y.

Just another transparent latch loaded with LD_X (or LD_Y), with output enable and with a super buffer at the output for driving the internal data bus.

It's a nice layout: a big PolySi pad connected to a bit of the internal data bus, then one bit of the POT_Y register east of the pad and one bit of the POT_X register west of the pad.

Layout for the registers is the same, just mirrored to make better use of the space on the silicon.

Then there are those two transparent latches between the register\counter block and the circuitry close to the POT pins, delaying PDET by one clock cycle:

Now the circuitry close to the POT_X pin (POT_Y seems to have an identical layout, just mirrored).

Schematic:

Those two FETs are working as a voltage comparator during sid_clk1 =1 and as a R\S flipflop with logic level outputs during sid_clk2 =1 .