Counter Logic

This is the logic that controls the counting direction:

Basically two cross-connected NOR gates forming an SR flip-flop which reacts on changes of the gate and the 0xFF signals. The latter triggers once the counter value becomes $ff.

So the counting direction will be set when the gate bit goes high and reset when gate goes low or when the counter reaches its maximum value.

This is the circuit that generates the signals controlling the counter:

R0 and cnt_up reflects the counting_direction signal state with respectively one and two cycles delay. The cnt_clk and cnt_clk_inv signals are derived through an XOR gate, that checks when counting_direction has changed from the previous clock cycle, and two NOR ports, that make one of the signals active during the sid_clk2 phase based on the XOR output. The result is that cnt_clk_inv is high only the cycle after counting_direction has changed.

Here is the input carry for bit 0 (the rest of the circuit is included in previous picture):

Again two cross-connected NOR gates forming an SR flip-flop which enables the counter when gate raises or on chip reset and disables it when the 0x00 signal triggers. Another NOR gate controls the clocking of the counter when it's active based on the release_reset and count=sustain signals.

The counter_enabled label is a bit misleading but I've left it untouched from the original layouts, sorry for the laziness.

One interesting "feature" of this logic is that when the counter is locked at $00, by switching on the gate and then turning it off before the counter is clocked again the envelope will count down wrapping to $ff until it gets back to $00. A similar trick, in the opposite direction, can be achieved when counter is at $ff.