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Data Bus
This is one of the eight data pins, the input logic on the left and the output logic on the right.
The input circuitry is based on NOR ports driven by the /Write and sid_rst signals:
The value at the gates of the two transistors on the right side of the picture (a being the one connected to Vcc and b the one connected to GND) are described by the following expressions:
- a = ¬(¬(¬(¬Dx ∨ sid_rst)) ∨ /write) = Dx ∧ ¬sid_rst ∧ ¬/write
- b = ¬(¬(¬Dx ∨ sid_rst) ∨ /write) = ¬(Dx ∧ ¬sid_rst) ∧ ¬/write
where Dx is the xth bit pin of the data bus. The resulting truth table is then:
Dx | sid_rst | /write | a | b | DBx |
---|---|---|---|---|---|
0 | 0 | 0 | 0 | 1 | 0 |
1 | 0 | 0 | 1 | 0 | 1 |
0 | 1 | 0 | 0 | 1 | 0 |
1 | 1 | 0 | 0 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | x |
1 | 0 | 1 | 0 | 0 | x |
0 | 1 | 1 | 0 | 0 | x |
1 | 1 | 1 | 0 | 0 | x |
When the /write line is high the input is disconnected from the data bus, otherwise the data from the pins is written to it, unless the sid_rst signal is high in which case a zero is forced unto the data bus. So during a reset all the writeable registers are initialized to zero. Writing to a read-only or a non-existant register only puts the input value on the data bus.
The output is based on NAND ports driven by the /Read signal:
The value at the gates of the two transistors on the right are described by the following expressions:
- a = ¬(¬(DBx ∧ ¬/read)) = DBx ∧ ¬/read
- b = ¬(¬(¬DBx ∧ ¬/read)) = ¬DBx ∧ ¬/read
where DBx is the data bus bit x. The resulting truth table is then:
DBx | /read | a | b | Dx |
---|---|---|---|---|
0 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 0 | 1 |
0 | 1 | 0 | 0 | x |
1 | 1 | 0 | 0 | x |
When the /read line is high the output is disconnected from the data pin, otherwise the value on the data bus can be read from the data pins. Reading from a write-only or a non-existant register returns the value present on the data bus, which is the one from the last valid read/write. This value fades to zero after some time, depending on the chip model and temperature.
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6581 DACs
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