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base repository: chipsalliance/chisel
base: main
head repository: rameloni/chisel
compare: tywaves-develop
Commits on Apr 18, 2024
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Annotate ports with Chisel type information in firrtl
- Create `TywavesAnnotation` (firrtl) case class to represent the annotation - Add companion object to generate `TywavesChiselAnnotation`s for Chisel circuit: it parses a chisel circuit, extracts the necessary information from each component, and annotates each FIRRTL target - Support annotation for IO ports - Add support for modules and data types (grounds, aggregates, and user-defined (only extended bundles)) - Support nested modules and data types - Create `AddTywavesAnnotations` phase to add the TywavesAnnotation to the elaborated Chisel circuit - Update `ChiselStage` to integrate `AddTywavesAnnotation` phase (run before `Convert` phase only if `withDebug` is true) - Added following tests: - Module tests: - Empty module - Module with submodule(s) - Modules with parameters and paremetrized modules (need to extract scala meta-programming information though) - BlackBoxes - Intrinsics - Classes - Ports test: - Explict Clock, SyncReset (Bool), AsyncReset and Reset - Implicit clock and reset - Ground types: Bool, UInt, SInt, Analog - Bundles: empty, anonymous, user-defined, nested - Vecs: 1-D, 2-D - MixedVec - Vecs of bundles - Bundles of vecs
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Commits on Apr 19, 2024
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Annotate registers and wires with Chisel type information in firrtl
- Added "createAnno" from DefWire, DefRef, DefRegInit case - Reorganize test structure making reusable modules for different bindings (IO, Reg, Wire) - Added following tests: - Ports tests: - Ports inside a submodule - Wire/reg tests: - Explict Clock, SyncReset (Bool), AsyncReset and Reset - Implicit clock and reset - Ground types: Bool, UInt, SInt - Analog (only wires) - Bundles: empty, anonymous, user-defined, nested - Vecs: 1-D, 2-D - MixedVec - Vecs of bundles - Bundles of vecs - Wires/regs inside a submodule
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Commits on Apr 21, 2024
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Refactor of TywavesAnnotationSpec test structure
- Move module and data types tests in different subdirectories - Add readmes with output samples of the annotations
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- Added "createAnno" from DefMemory, DefSeqMemory, FirrtlMemory and DefMemPort case - Implement "createAnnoMem" to create a TyeavesAnnotation for memory (a memory does not extend the Data type) - Return empty annotations from Connect, DefInvalid - Add warning message for "Unhandled circuit commands" - Added the following tests: - ROM of ground type - SyncReadMem (when UNUSED) of ground type, aggregate types (bundle) - Mem (when UNUSED) of ground type, aggregate types (bundle) - SRAM of ground type (with different combs of ports), aggregate types - SyncReadMem (when USED) of ground type, aggregate types (this instantiate MPORT) - Mem (when USED) of ground type, aggregate types (this instantiate MPORT)
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Commits on Apr 22, 2024
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[Fix tywaves] type name a annotation for innertype in memories (case …
…of Vecs) - Added the following tests: - Masked memories (SyncReadMem, Mem, SRAM)
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Commits on Apr 24, 2024
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Annotate types with the parameters (name, type, value) in the scala c…
…onstructor (it works for any scala class) [Fix tywaves] Fix annotation issue for first parameter of the constructor Sometimes the first parameters was skipped. The `getConstructorParams` was dropping the first element of the list assuming that it contained the class itself and not a parameter. This assumption worked only for some cases ("$outer" is not always present in first position). Now the method is improved by doing a filter map (collect). Update report output samples in tests readmes Annotate types with parameters in the scala constructor (it works for any scala class) - Create a case class (`ClassParam`) to represent the parameters of a class in the firrtl annotation - Update `TywavesAnnotation` with `params: Option[Seq[ClassParam]]`. Some classes may not have any parameter - Implement `getConstructorParams()` to get params of a constructor of any scala class. It uses scala reflection. - Added the following tests: - Test getConstructorParams() for: - classes - case classes - private, protected and public fields in the constructor: name, type and value accessible - fields in the body of a class (expected behaviour not accessible) - parameters in the constructor (no val): only name and type accessible - Updated the following tests: - Vec tests of DataTypesSpec: chisel Vecs have a length parameter in the constructor - Mem tests: memories contain constructs with parameters in their constructors - Module tests: update the module with parameters test
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Commits on Apr 25, 2024
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Fix behaviour of getConstructorParams when the value of a parameter i…
…s type of chisel3.Data Now it returns only the value without the complete name (packageName.type.name) of the parameter. - Fix hasParams: sometimes some parameters of a class were not detected. - Added the following tests: - Circuit with parameters (scala basic types, scala classes, and chisel types) - Bundles with parameters (scala basic types, scala classes, and chisel types) - Updated tests (scala fmt and bug fix): - TypeAnnotationMemSpec - TypeAnnotationModuleSpec - TypeAnnotationDataTypesSpec - Fix scalafmt errors
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Commits on May 8, 2024
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Commits on Jun 2, 2024
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Fix TypeAnnotationMemSpec test. Run scala fmt
rameloni committedJun 2, 2024 Loading Loading status checks…Configuration menu - View commit details
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Commits on Jun 27, 2024
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Merge branch 'chipsalliance:main' into tywaves-annotations
rameloni authoredJun 27, 2024 Loading Loading status checks…Configuration menu - View commit details
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Commits on Jul 9, 2024
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Merge branch 'chipsalliance:main' into tywaves-annotations
rameloni authoredJul 9, 2024 Loading Loading status checks…Configuration menu - View commit details
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Rename tywaves package in tywavesinternal
Solve any conflict with the package in tywaves-chisel-api. Fix rameloni/tywaves-chisel#27
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Annotate temporary nodes in when statements
rameloni committedJul 9, 2024 Loading Loading status checks…Configuration menu - View commit details
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Commits on Jul 11, 2024
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Add circuit test with ChiselEnums
rameloni committedJul 11, 2024 Loading Loading status checks…Configuration menu - View commit details
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