Annotate Chisel Memories

- Added "createAnno" from DefMemory, DefSeqMemory, FirrtlMemory and DefMemPort case
- Implement "createAnnoMem" to create a TyeavesAnnotation for memory (a memory does not extend the Data type)
- Return empty annotations from Connect, DefInvalid
- Add warning message for "Unhandled circuit commands"
- Added the following tests:
	- ROM of ground type
	- SyncReadMem (when UNUSED) of ground type, aggregate types (bundle)
	- Mem (when UNUSED) of ground type, aggregate types (bundle)
	- SRAM of ground type (with different combs of ports), aggregate types
	- SyncReadMem (when USED) of ground type, aggregate types (this instantiate MPORT)
        - Mem (when USED) of ground type, aggregate types (this instantiate MPORT)

Author: rameloni

core/src/main/scala/chisel3/tywaves/TywavesAnnotation.scala

@@ -2,6 +2,7 @@ package chisel3.tywaves
 
 import chisel3.{Aggregate, Bits, Bundle, Data, Record, Vec, VecLike}
 import chisel3.experimental.{annotate, BaseModule, ChiselAnnotation}
+import chisel3.internal.HasId
 import chisel3.internal.firrtl.Converter.convert
 import chisel3.internal.firrtl.ir._
 import firrtl.annotations.{Annotation, IsMember, ReferenceTarget, SingleTargetAnnotation}
@@ -61,23 +62,32 @@ object TywavesChiselAnnotation {
   def generate(port: Port, typeAliases: Seq[String]): Seq[ChiselAnnotation] = createAnno(port.id)
 
   def generate(command: Command, typeAliases: Seq[String]): Seq[ChiselAnnotation] = {
+    def createAnnoMem(target: HasId, binding: String, size: BigInt, innerType: Data): Seq[ChiselAnnotation] = {
+      val name = s"$binding[${innerType.typeName}[$size]]"
+      // TODO: what if innerType is a Vec or a Bundle?
+
+      Seq(new ChiselAnnotation {
+        override def toFirrtl: Annotation = TywavesAnnotation(target.toTarget, name)
+      }) //++ createAnno(chisel3.Wire(innerType))
+    }
 
     command match {
       case e: DefPrim[_] => ???
-      case e @ DefWire(info, id)                                                                  => createAnno(id)
-      case e @ DefReg(info, id, clock)                                                            => createAnno(id)
-      case e @ DefRegInit(info, id, clock, reset, init)                                           => createAnno(id)
-      case e @ DefMemory(info, id, t, size)                                                       => ???
-      case e @ DefSeqMemory(info, id, t, size, ruw)                                               => ???
-      case e @ FirrtlMemory(info, id, t, size, readPortNames, writePortNames, readwritePortNames) => ???
-      case e: DefMemPort[_] => ???
-      case Connect(info, loc, exp)                                  => println(s"Connect: $info, $loc, $exp"); Seq.empty
+      case e @ DefWire(info, id)                        => createAnno(id)
+      case e @ DefReg(info, id, clock)                  => createAnno(id)
+      case e @ DefRegInit(info, id, clock, reset, init) => createAnno(id)
+      case e @ DefMemory(info, id, t, size)             => createAnnoMem(id, id.getClass.getSimpleName, size, t)
+      case e @ DefSeqMemory(info, id, t, size, ruw)     => createAnnoMem(id, id.getClass.getSimpleName, size, t)
+      case e @ FirrtlMemory(info, id, t, size, readPortNames, writePortNames, readwritePortNames) =>
+        createAnnoMem(id, id.getClass.getSimpleName, size, t)
+      case e @ DefMemPort(info, id, source, dir, idx, clock)        => createAnno(id)
+      case Connect(info, loc, exp)                                  => Seq.empty // TODO: check connect
       case PropAssign(info, loc, exp)                               => ???
       case Attach(info, locs)                                       => ???
-      case DefInvalid(info, arg)                                    => ???
-      case e @ DefInstance(info, id, _)                             => Seq.empty // Seq(createAnno(id))
+      case DefInvalid(info, arg)                                    => Seq.empty // TODO: check invalid
+      case e @ DefInstance(info, id, _)                             => Seq.empty // TODO: check instance
       case e @ DefInstanceChoice(info, _, default, option, choices) => ???
-      case e @ DefObject(info, _, className)                        => println(s"DefObject: $info, $className"); Seq.empty
+      case e @ DefObject(info, _, className)                        => Seq.empty // TODO: check object
       case e @ Stop(_, info, clock, ret)                            => ???
       case e @ Printf(_, info, clock, pable)                        => ???
       case e @ ProbeDefine(sourceInfo, sink, probeExpr)             => ???
@@ -86,11 +96,12 @@ object TywavesChiselAnnotation {
       case e @ ProbeForce(sourceInfo, clock, cond, probe, value)    => ???
       case e @ ProbeRelease(sourceInfo, clock, cond, probe)         => ???
       case e @ Verification(_, op, info, clk, pred, pable)          => ???
-      case _                                                        => Seq.empty
+      case e =>
+        println(s"Unknown command: $e") // TODO: replace with logger
+        Seq.empty
     }
     // TODO: Add tywaves annotation
 
-//    ???
   }
 
   /**

src/test/scala/circtTests/tywavesTests/TywavesAnnotationCircuits.scala

@@ -224,4 +224,54 @@ object TywavesAnnotationCircuits {
     }
   }
 
+  object MemCircuits {
+    // Test memory ROM: https://www.chisel-lang.org/docs/explanations/memories#rom
+    class ROMs {
+
+      import chisel3.experimental.BundleLiterals._
+
+      val romFromVec:     Vec[UInt] = Wire(Vec(4, UInt(8.W)))
+      val romFromVecInit: Vec[UInt] = VecInit(1.U, 2.U, 4.U, 8.U)
+      for (i <- 0 until 4) {
+        romFromVec(i) := romFromVecInit(i)
+      }
+      val bundle = new Bundle {
+        val a: UInt = UInt(8.W)
+      }
+      val romOfBundles =
+        VecInit(bundle.Lit(_.a -> 1.U), bundle.Lit(_.a -> 2.U), bundle.Lit(_.a -> 4.U), bundle.Lit(_.a -> 8.U))
+    }
+
+    // TODO: having children in the roms object does not imply the same hierarchy in firrtl (roms is pure scala)
+    class TopCircuitROM extends RawModule {
+      val roms = new ROMs
+    }
+
+    class TopCircuitSyncMem[T <: Data](gen: T, withConnection: Boolean /* If true connect memPort */ ) extends Module {
+      val mem = SyncReadMem(4, gen)
+      if (withConnection) {
+        val idx = IO(Input(UInt(2.W)))
+        val in = IO(Input(gen))
+        val out = IO(Output(gen))
+        mem.write(idx, in)
+        out := mem.read(idx)
+      }
+    }
+
+    class TopCircuitMem[T <: Data](gen: T, withConnection: Boolean) extends Module {
+      val mem = Mem(4, gen)
+      if (withConnection) {
+        val idx = IO(Input(UInt(2.W)))
+        val in = IO(Input(gen))
+        val out = IO(Output(gen))
+        mem(idx) := in
+        out := mem(idx)
+      }
+    }
+
+    class TopCircuitSRAM[T <: Data](gen: T, size: Int, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)
+        extends Module {
+      val mem = SRAM(size, gen, numReadPorts, numWritePorts, numReadwritePorts)
+    }
+  }
 }