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ramelonirameloni
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Rename tywaves package in tywavesinternal
Solve any conflict with the package in tywaves-chisel-api. Fix rameloni/tywaves-chisel#27
1 parent 44b03b3 commit 2d57816

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11 files changed

+131
-132
lines changed

11 files changed

+131
-132
lines changed

‎core/src/main/scala/chisel3/tywaves/TywavesAnnotation.scala renamed to ‎core/src/main/scala/chisel3/tywavesinternal/TywavesAnnotation.scala

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
package chisel3.tywaves
1+
package chisel3.tywavesinternal
22

33
import chisel3.{Data, Record, Vec, VecLike}
44
import chisel3.experimental.{BaseModule, ChiselAnnotation}
@@ -88,7 +88,6 @@ object TywavesChiselAnnotation {
8888
override def toFirrtl: Annotation = TywavesAnnotation(target.toTarget, name, None)
8989
}) //++ createAnno(chisel3.Wire(innerType))
9090
}
91-
9291
command match {
9392
case e: DefPrim[_] => Seq.empty // TODO: check prim
9493
case e @ DefWire(info, id) => createAnno(id)

‎src/main/scala/chisel3/stage/phases/AddTywavesAnnotations.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
package chisel3.stage.phases
22

33
import chisel3.stage.ChiselCircuitAnnotation
4-
import chisel3.tywaves.TywavesChiselAnnotation
4+
import chisel3.tywavesinternal.TywavesChiselAnnotation
55
import firrtl.AnnotationSeq
66
import firrtl.options.{Dependency, Phase}
77

‎src/test/scala/circtTests/tywavesTests/TywavesAnnotationCircuits.scala

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,13 @@ import chisel3._
44
import chisel3.experimental.{Analog, IntrinsicModule}
55
import chisel3.experimental.hierarchy.{instantiable, Definition, Instance}
66
import chisel3.stage.ChiselGeneratorAnnotation
7-
import chisel3.tywaves.{ClassParam, TywavesChiselAnnotation}
7+
import chisel3.tywavesinternal.{ClassParam, TywavesChiselAnnotation}
88
import chisel3.util.{MixedVec, SRAM, SRAMInterface}
99
import circt.stage.ChiselStage
1010
import org.scalatest.AppendedClues.convertToClueful
1111
import org.scalatest.matchers.should.Matchers
1212

13-
/** Utility functions for testing [[chisel3.tywaves.TywavesAnnotation]] */
13+
/** Utility functions for testing [[chisel3.tywavesinternal.TywavesAnnotation]] */
1414
object TestUtils extends Matchers {
1515

1616
def countSubstringOccurrences(mainString: String, subString: String): Int = {
@@ -48,7 +48,7 @@ object TestUtils extends Matchers {
4848

4949
def checkAnno(expectedMatches: Seq[(String, Int)], refString: String, includeConstructor: Boolean = false): Unit = {
5050
def totalAnnoCheck(n: Int): (String, Int) =
51-
(""""class":"chisel3.tywaves.TywavesAnnotation"""", if (includeConstructor) n else n + 1)
51+
(""""class":"chisel3.tywavesinternal.TywavesAnnotation"""", if (includeConstructor) n else n + 1)
5252

5353
(expectedMatches :+ totalAnnoCheck(expectedMatches.map(_._2).sum)).foreach {
5454
case (pattern, count) =>

‎src/test/scala/circtTests/tywavesTests/dataTypesTests/README.md

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -20,27 +20,27 @@ class TopCircuitClockReset extends RawModule {
2020
FIRRTL version 4.0.0
2121
circuit TopCircuitClockReset :%[[
2222
{
23-
"class":"chisel3.tywaves.TywavesAnnotation",
23+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
2424
"target":"~TopCircuitClockReset|TopCircuitClockReset",
2525
"typeName":"TopCircuitClockReset"
2626
},
2727
{
28-
"class":"chisel3.tywaves.TywavesAnnotation",
28+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
2929
"target":"~TopCircuitClockReset|TopCircuitClockReset>clock",
3030
"typeName":"IO[Clock]"
3131
},
3232
{
33-
"class":"chisel3.tywaves.TywavesAnnotation",
33+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
3434
"target":"~TopCircuitClockReset|TopCircuitClockReset>syncReset",
3535
"typeName":"IO[Bool]"
3636
},
3737
{
38-
"class":"chisel3.tywaves.TywavesAnnotation",
38+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
3939
"target":"~TopCircuitClockReset|TopCircuitClockReset>reset",
4040
"typeName":"IO[Reset]"
4141
},
4242
{
43-
"class":"chisel3.tywaves.TywavesAnnotation",
43+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
4444
"target":"~TopCircuitClockReset|TopCircuitClockReset>asyncReset",
4545
"typeName":"IO[AsyncReset]"
4646
}
@@ -64,17 +64,17 @@ class TopCircuitImplicitClockReset extends Module
6464
FIRRTL version 4.0.0
6565
circuit TopCircuitImplicitClockReset :%[[
6666
{
67-
"class":"chisel3.tywaves.TywavesAnnotation",
67+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
6868
"target":"~TopCircuitImplicitClockReset|TopCircuitImplicitClockReset",
6969
"typeName":"TopCircuitImplicitClockReset"
7070
},
7171
{
72-
"class":"chisel3.tywaves.TywavesAnnotation",
72+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
7373
"target":"~TopCircuitImplicitClockReset|TopCircuitImplicitClockReset>clock",
7474
"typeName":"IO[Clock]"
7575
},
7676
{
77-
"class":"chisel3.tywaves.TywavesAnnotation",
77+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
7878
"target":"~TopCircuitImplicitClockReset|TopCircuitImplicitClockReset>reset",
7979
"typeName":"IO[Bool]"
8080
}
@@ -103,32 +103,32 @@ class TopCircuitGroundTypes extends RawModule {
103103
```fir
104104
circuit TopCircuitGroundTypes :%[[
105105
{
106-
"class":"chisel3.tywaves.TywavesAnnotation",
106+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
107107
"target":"~TopCircuitGroundTypes|TopCircuitGroundTypes",
108108
"typeName":"TopCircuitGroundTypes"
109109
},
110110
{
111-
"class":"chisel3.tywaves.TywavesAnnotation",
111+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
112112
"target":"~TopCircuitGroundTypes|TopCircuitGroundTypes>uint",
113113
"typeName":"IO[UInt<8>]"
114114
},
115115
{
116-
"class":"chisel3.tywaves.TywavesAnnotation",
116+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
117117
"target":"~TopCircuitGroundTypes|TopCircuitGroundTypes>sint",
118118
"typeName":"IO[SInt<8>]"
119119
},
120120
{
121-
"class":"chisel3.tywaves.TywavesAnnotation",
121+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
122122
"target":"~TopCircuitGroundTypes|TopCircuitGroundTypes>bool",
123123
"typeName":"IO[Bool]"
124124
},
125125
{
126-
"class":"chisel3.tywaves.TywavesAnnotation",
126+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
127127
"target":"~TopCircuitGroundTypes|TopCircuitGroundTypes>analog",
128128
"typeName":"IO[Analog<1>]"
129129
},
130130
{
131-
"class":"chisel3.tywaves.TywavesAnnotation",
131+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
132132
"target":"~TopCircuitGroundTypes|TopCircuitGroundTypes>bits",
133133
"typeName":"IO[UInt<8>]"
134134
}
@@ -165,37 +165,37 @@ class TopCircuitBundles extends RawModule {
165165
```fir
166166
circuit TopCircuitBundles :%[[
167167
{
168-
"class":"chisel3.tywaves.TywavesAnnotation",
168+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
169169
"target":"~TopCircuitBundles|TopCircuitBundles",
170170
"typeName":"TopCircuitBundles"
171171
},
172172
{
173-
"class":"chisel3.tywaves.TywavesAnnotation",
173+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
174174
"target":"~TopCircuitBundles|TopCircuitBundles>a",
175175
"typeName":"IO[AnonymousBundle]"
176176
},
177177
{
178-
"class":"chisel3.tywaves.TywavesAnnotation",
178+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
179179
"target":"~TopCircuitBundles|TopCircuitBundles>b",
180180
"typeName":"IO[MyEmptyBundle]"
181181
},
182182
{
183-
"class":"chisel3.tywaves.TywavesAnnotation",
183+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
184184
"target":"~TopCircuitBundles|TopCircuitBundles>c.c",
185185
"typeName":"IO[Bool]"
186186
},
187187
{
188-
"class":"chisel3.tywaves.TywavesAnnotation",
188+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
189189
"target":"~TopCircuitBundles|TopCircuitBundles>c.b",
190190
"typeName":"IO[SInt<8>]"
191191
},
192192
{
193-
"class":"chisel3.tywaves.TywavesAnnotation",
193+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
194194
"target":"~TopCircuitBundles|TopCircuitBundles>c.a",
195195
"typeName":"IO[UInt<8>]"
196196
},
197197
{
198-
"class":"chisel3.tywaves.TywavesAnnotation",
198+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
199199
"target":"~TopCircuitBundles|TopCircuitBundles>c",
200200
"typeName":"IO[MyBundle]"
201201
}
@@ -226,57 +226,57 @@ class TopCircuitBundlesNested extends RawModule {
226226
FIRRTL version 4.0.0
227227
circuit TopCircuitBundlesNested :%[[
228228
{
229-
"class":"chisel3.tywaves.TywavesAnnotation",
229+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
230230
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested",
231231
"typeName":"TopCircuitBundlesNested"
232232
},
233233
{
234-
"class":"chisel3.tywaves.TywavesAnnotation",
234+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
235235
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.c.c",
236236
"typeName":"IO[Bool]"
237237
},
238238
{
239-
"class":"chisel3.tywaves.TywavesAnnotation",
239+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
240240
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.c.b",
241241
"typeName":"IO[SInt<8>]"
242242
},
243243
{
244-
"class":"chisel3.tywaves.TywavesAnnotation",
244+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
245245
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.c.a",
246246
"typeName":"IO[UInt<8>]"
247247
},
248248
{
249-
"class":"chisel3.tywaves.TywavesAnnotation",
249+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
250250
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.c",
251251
"typeName":"IO[MyBundle]"
252252
},
253253
{
254-
"class":"chisel3.tywaves.TywavesAnnotation",
254+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
255255
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.b.c",
256256
"typeName":"IO[Bool]"
257257
},
258258
{
259-
"class":"chisel3.tywaves.TywavesAnnotation",
259+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
260260
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.b.b",
261261
"typeName":"IO[SInt<8>]"
262262
},
263263
{
264-
"class":"chisel3.tywaves.TywavesAnnotation",
264+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
265265
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.b.a",
266266
"typeName":"IO[UInt<8>]"
267267
},
268268
{
269-
"class":"chisel3.tywaves.TywavesAnnotation",
269+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
270270
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.b",
271271
"typeName":"IO[MyBundle]"
272272
},
273273
{
274-
"class":"chisel3.tywaves.TywavesAnnotation",
274+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
275275
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a.a",
276276
"typeName":"IO[Bool]"
277277
},
278278
{
279-
"class":"chisel3.tywaves.TywavesAnnotation",
279+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
280280
"target":"~TopCircuitBundlesNested|TopCircuitBundlesNested>a",
281281
"typeName":"IO[MyNestedBundle]"
282282
}
@@ -315,17 +315,17 @@ class TopCircuitVecs(bindingChoice: BindingChoice) extends TywavesTestModule(bin
315315
FIRRTL version 4.0.0
316316
circuit TopCircuitVecs :%[[
317317
{
318-
"class":"chisel3.tywaves.TywavesAnnotation",
318+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
319319
"target":"~TopCircuitVecs|TopCircuitVecs",
320320
"typeName":"TopCircuitVecs"
321321
},
322322
{
323-
"class":"chisel3.tywaves.TywavesAnnotation",
323+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
324324
"target":"~TopCircuitVecs|TopCircuitVecs>a[0]",
325325
"typeName":"IO[SInt<23>]"
326326
},
327327
{
328-
"class":"chisel3.tywaves.TywavesAnnotation",
328+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
329329
"target":"~TopCircuitVecs|TopCircuitVecs>a",
330330
"typeName":"IO[SInt<23>[5]]",
331331
"params":[
@@ -336,12 +336,12 @@ circuit TopCircuitVecs :%[[
336336
]
337337
},
338338
{
339-
"class":"chisel3.tywaves.TywavesAnnotation",
339+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
340340
"target":"~TopCircuitVecs|TopCircuitVecs>b[0][0]",
341341
"typeName":"IO[SInt<23>]"
342342
},
343343
{
344-
"class":"chisel3.tywaves.TywavesAnnotation",
344+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
345345
"target":"~TopCircuitVecs|TopCircuitVecs>b[0]",
346346
"typeName":"IO[SInt<23>[3]]",
347347
"params":[
@@ -352,7 +352,7 @@ circuit TopCircuitVecs :%[[
352352
]
353353
},
354354
{
355-
"class":"chisel3.tywaves.TywavesAnnotation",
355+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
356356
"target":"~TopCircuitVecs|TopCircuitVecs>b",
357357
"typeName":"IO[SInt<23>[3][5]]",
358358
"params":[
@@ -363,17 +363,17 @@ circuit TopCircuitVecs :%[[
363363
]
364364
},
365365
{
366-
"class":"chisel3.tywaves.TywavesAnnotation",
366+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
367367
"target":"~TopCircuitVecs|TopCircuitVecs>c[0].x",
368368
"typeName":"IO[UInt<8>]"
369369
},
370370
{
371-
"class":"chisel3.tywaves.TywavesAnnotation",
371+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
372372
"target":"~TopCircuitVecs|TopCircuitVecs>c[0]",
373373
"typeName":"IO[AnonymousBundle]"
374374
},
375375
{
376-
"class":"chisel3.tywaves.TywavesAnnotation",
376+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
377377
"target":"~TopCircuitVecs|TopCircuitVecs>c",
378378
"typeName":"IO[AnonymousBundle[5]]",
379379
"params":[
@@ -384,17 +384,17 @@ circuit TopCircuitVecs :%[[
384384
]
385385
},
386386
{
387-
"class":"chisel3.tywaves.TywavesAnnotation",
387+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
388388
"target":"~TopCircuitVecs|TopCircuitVecs>d.0",
389389
"typeName":"IO[UInt<3>]"
390390
},
391391
{
392-
"class":"chisel3.tywaves.TywavesAnnotation",
392+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
393393
"target":"~TopCircuitVecs|TopCircuitVecs>d.1",
394394
"typeName":"IO[SInt<10>]"
395395
},
396396
{
397-
"class":"chisel3.tywaves.TywavesAnnotation",
397+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
398398
"target":"~TopCircuitVecs|TopCircuitVecs>d",
399399
"typeName":"IO[MixedVec]"
400400
}
@@ -423,17 +423,17 @@ class TopCircuitBundleWithVec extends RawModule {
423423
```fir
424424
circuit TopCircuitBundleWithVec :%[[
425425
{
426-
"class":"chisel3.tywaves.TywavesAnnotation",
426+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
427427
"target":"~TopCircuitBundleWithVec|TopCircuitBundleWithVec",
428428
"typeName":"TopCircuitBundleWithVec"
429429
},
430430
{
431-
"class":"chisel3.tywaves.TywavesAnnotation",
431+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
432432
"target":"~TopCircuitBundleWithVec|TopCircuitBundleWithVec>a.vec[0]",
433433
"typeName":"IO[UInt<8>]"
434434
},
435435
{
436-
"class":"chisel3.tywaves.TywavesAnnotation",
436+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
437437
"target":"~TopCircuitBundleWithVec|TopCircuitBundleWithVec>a.vec",
438438
"typeName":"IO[UInt<8>[5]]",
439439
"params":[
@@ -444,7 +444,7 @@ circuit TopCircuitBundleWithVec :%[[
444444
]
445445
},
446446
{
447-
"class":"chisel3.tywaves.TywavesAnnotation",
447+
"class":"chisel3.tywavesinternal.TywavesAnnotation",
448448
"target":"~TopCircuitBundleWithVec|TopCircuitBundleWithVec>a",
449449
"typeName":"IO[AnonymousBundle]"
450450
}

‎src/test/scala/circtTests/tywavesTests/dataTypesTests/TypeAnnotationDataTypesSpec.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ package circtTests.tywavesTests.dataTypesTests
22

33
import chisel3._
44
import chisel3.stage.ChiselGeneratorAnnotation
5-
import chisel3.tywaves.ClassParam
5+
import chisel3.tywavesinternal.ClassParam
66
import circt.stage.ChiselStage
77
import org.scalatest.funspec.AnyFunSpec
88
import org.scalatest.matchers.should.Matchers

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