Merge branch 'chipsalliance:main' into tywaves-annotations

Author: rameloni

build.sbt

@@ -67,7 +67,8 @@ lazy val warningSuppression = Seq(
     // This is deprecated for external users but not internal use
     "cat=deprecation&origin=firrtl\\.options\\.internal\\.WriteableCircuitAnnotation:s",
     "cat=deprecation&origin=chisel3\\.util\\.experimental\\.BoringUtils.*:s",
-    "cat=deprecation&origin=chisel3\\.experimental\\.IntrinsicModule:s"
+    "cat=deprecation&origin=chisel3\\.experimental\\.IntrinsicModule:s",
+    "cat=deprecation&origin=chisel3\\.ltl.*:s"
   ).mkString(",")
 )
 

core/src/main/scala/chisel3/Aggregate.scala

@@ -114,25 +114,52 @@ sealed abstract class Aggregate extends Data {
     }
   }
 
-  private[chisel3] override def connectFromBits(
-    that: Bits
-  )(
-    implicit sourceInfo: SourceInfo
-  ): Unit = {
-    var i = 0
-    val bits = if (that.isLit) that else WireDefault(UInt(this.width), that) // handles width padding
-    for (x <- flatten) {
-      val fieldWidth = x.getWidth
-      if (fieldWidth > 0) {
-        x.connectFromBits(bits(i + fieldWidth - 1, i))
-        i += fieldWidth
-      } else {
-        // There's a zero-width field in this bundle.
-        // Zero-width fields can't really be assigned to, but the frontend complains if there are uninitialized fields,
-        // so we assign it to DontCare. We can't use connectFromBits() on DontCare, so use := instead.
-        x := DontCare
+  // Return a literal of the same type from a Seq of literals for each leaf
+  private[chisel3] final def _makeLitFromLeaves(elems: Seq[Element])(implicit sourceInfo: SourceInfo): Data = {
+    // We could use virtual methods instead of matching on concrete subtypes,
+    // but the difference for Record vs Vec is so small, it doesn't seem worth it
+    val clone: Aggregate = this.cloneTypeFull
+    val mapping = clone.flatten.view
+      .zip(elems)
+      .map {
+        case (thisElt, litElt) =>
+          val litArg = litElt.topBindingOpt match {
+            case Some(ElementLitBinding(value)) => value
+            case _                              => throwException(s"Internal Error! For field $thisElt, given non-literal $litElt!")
+          }
+          thisElt -> litArg
+      }
+    val binding = clone match {
+      case r: Record => BundleLitBinding(mapping.to(Map))
+      case v: Vec[_] => VecLitBinding(mapping.to(VectorMap))
+    }
+    clone.bind(binding)
+    clone
+  }
+
+  override private[chisel3] def _fromUInt(that: UInt)(implicit sourceInfo: SourceInfo): Data = {
+    val _asUInt = _resizeToWidth(that, this.widthOption)(identity)
+    // If that is a literal and all constituent Elements can be represented as literals, return a literal
+    val ((_, allLit), rvalues) = {
+      this.flatten.toList.mapAccumulate((0, _asUInt.isLit)) {
+        case ((lo, literal), elt) =>
+          val hi = lo + elt.getWidth
+          // Chisel only supports zero width extraction if hi = -1 and lo = 0, so do it manually
+          val _extracted = if (elt.getWidth == 0) 0.U(0.W) else _asUInt(hi - 1, lo)
+          // _fromUInt returns Data but we know that it is an Element
+          val rhs = elt._fromUInt(_extracted).asInstanceOf[Element]
+          ((hi, literal && rhs.isLit), rhs)
       }
     }
+    if (allLit) {
+      this._makeLitFromLeaves(rvalues)
+    } else {
+      val _wire = Wire(this.cloneTypeFull)
+      for ((l, r) <- _wire.flatten.zip(rvalues)) {
+        l := r
+      }
+      _wire
+    }
   }
 }
 
@@ -215,8 +242,10 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
 
     val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection)
     sample_element.bind(SampleElementBinding(this), resolvedDirection)
+    // Share same object for binding of all children.
+    val childBinding = ChildBinding(this)
     for (child <- elementsIterator) { // assume that all children are the same
-      child.bind(ChildBinding(this), resolvedDirection)
+      child.bind(childBinding, resolvedDirection)
     }
 
     // Since all children are the same, we can just use the sample_element rather than all children
@@ -512,7 +541,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
               if (m < n) Some(index -> lit) else None
             case (KnownWidth(_), _) =>
               None
-            case (UnknownWidth(), _) =>
+            case (UnknownWidth, _) =>
               None
             case _ =>
               Some(index -> lit)
@@ -632,26 +661,6 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
 
 object VecInit extends SourceInfoDoc {
 
-  /** Gets the correct connect operation (directed hardware assign or bulk connect) for element in Vec.
-    */
-  private def getConnectOpFromDirectionality[T <: Data](
-    proto: T
-  )(
-    implicit sourceInfo: SourceInfo
-  ): (T, T) => Unit = proto.direction match {
-    case ActualDirection.Input | ActualDirection.Output | ActualDirection.Unspecified =>
-      // When internal wires are involved, driver / sink must be specified explicitly, otherwise
-      // the system is unable to infer which is driver / sink
-      (x, y) => x := y
-    case ActualDirection.Bidirectional(_) =>
-      // For bidirectional, must issue a bulk connect so subelements are resolved correctly.
-      // Bulk connecting two wires may not succeed because Chisel frontend does not infer
-      // directions.
-      (x, y) => x <> y
-    case ActualDirection.Empty =>
-      (x, y) => x <> y
-  }
-
   /** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]]
     * nodes.
     *
@@ -677,10 +686,9 @@ object VecInit extends SourceInfoDoc {
     elts.foreach(requireIsHardware(_, "vec element"))
 
     val vec = Wire(Vec(elts.length, cloneSupertype(elts, "Vec")))
-    val op = getConnectOpFromDirectionality(vec.head)
 
-    (vec.zip(elts)).foreach { x =>
-      op(x._1, x._2)
+    for ((lhs, rhs) <- vec.zip(elts)) {
+      lhs :<>= rhs
     }
     vec
   }
@@ -746,12 +754,11 @@ object VecInit extends SourceInfoDoc {
 
     val tpe = cloneSupertype(flatElts, "Vec.tabulate")
     val myVec = Wire(Vec(n, Vec(m, tpe)))
-    val op = getConnectOpFromDirectionality(myVec.head.head)
     for {
       (xs1D, ys1D) <- myVec.zip(elts)
-      (x, y) <- xs1D.zip(ys1D)
+      (lhs, rhs) <- xs1D.zip(ys1D)
     } {
-      op(x, y)
+      lhs :<>= rhs
     }
     myVec
   }
@@ -786,14 +793,13 @@ object VecInit extends SourceInfoDoc {
 
     val tpe = cloneSupertype(flatElts, "Vec.tabulate")
     val myVec = Wire(Vec(n, Vec(m, Vec(p, tpe))))
-    val op = getConnectOpFromDirectionality(myVec.head.head.head)
 
     for {
       (xs2D, ys2D) <- myVec.zip(elts)
       (xs1D, ys1D) <- xs2D.zip(ys2D)
-      (x, y) <- xs1D.zip(ys1D)
+      (lhs, rhs) <- xs1D.zip(ys1D)
     } {
-      op(x, y)
+      lhs :<>= rhs
     }
 
     myVec
@@ -1066,18 +1072,20 @@ abstract class Record extends Aggregate {
 
     checkForAndReportDuplicates()
 
-    // This check is for making sure that elements always returns the
-    // same object, which will not be the case if the user makes it a
-    // def inside the Record. Checking elementsIterator against itself
-    // is not useful for this check because it's a lazy val which will
-    // always return the same thing.
+    // Share same object for binding of all children.
+    val childBinding = ChildBinding(this)
     for (((_, child), sameChild) <- this.elements.iterator.zip(this.elementsIterator)) {
+      // This check is for making sure that elements always returns the
+      // same object, which will not be the case if the user makes it a
+      // def inside the Record. Checking elementsIterator against itself
+      // is not useful for this check because it's a lazy val which will
+      // always return the same thing.
       if (child != sameChild) {
         throwException(
           s"${this.className} does not return the same objects when calling .elements multiple times. Did you make it a def by mistake?"
         )
       }
-      child.bind(ChildBinding(this), resolvedDirection)
+      child.bind(childBinding, resolvedDirection)
 
       // Update the flipped tracker based on the flipped-ness of this specific child element
       _containsAFlipped |= child.containsAFlipped
@@ -1222,7 +1230,7 @@ abstract class Record extends Aggregate {
       case (field, value) =>
         field.width match {
           // If width is unknown, then it is set by the literal value.
-          case UnknownWidth() => field -> value
+          case UnknownWidth => field -> value
           case width @ KnownWidth(widthValue) =>
             val valuex = if (widthValue < value.width.get) {
               // For legacy reasons, 0.U is 1-bit, don't warn when it comes up as a literal value for 0-bit Bundle lit field.

core/src/main/scala/chisel3/Bits.scala

@@ -4,7 +4,7 @@ package chisel3
 
 import scala.language.experimental.macros
 import chisel3.experimental.{requireIsHardware, SourceInfo}
-import chisel3.internal.{throwException, BaseModule}
+import chisel3.internal.{_resizeToWidth, throwException, BaseModule}
 import chisel3.internal.Builder.pushOp
 import chisel3.internal.firrtl.ir._
 import chisel3.internal.sourceinfo.{
@@ -80,16 +80,16 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
       case KnownWidth(x) =>
         require(x >= n, s"Can't tail($n) for width $x < $n")
         Width(x - n)
-      case UnknownWidth() => Width()
+      case UnknownWidth => Width()
     }
     binop(sourceInfo, UInt(width = w), TailOp, n)
   }
 
   /** @group SourceInfoTransformMacro */
   def do_head(n: Int)(implicit sourceInfo: SourceInfo): UInt = {
     width match {
-      case KnownWidth(x)  => require(x >= n, s"Can't head($n) for width $x < $n")
-      case UnknownWidth() =>
+      case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n")
+      case UnknownWidth  => ()
     }
     binop(sourceInfo, UInt(Width(n)), HeadOp, n)
   }
@@ -695,7 +695,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
     resultWidth match {
       // To emulate old FIRRTL behavior where minimum width is 1, we need to insert pad(_, 1) whenever
       // the width is or could be 0. Thus we check if it is known to be 0 or is unknown.
-      case w @ (KnownWidth(0) | UnknownWidth()) =>
+      case w @ (KnownWidth(0) | UnknownWidth) =>
         // Because we are inserting an extra op but we want stable emission (so the user can diff the output),
         // we need to seed a name to avoid name collisions.
         op.autoSeed("_shrLegacyWidthFixup")
@@ -705,7 +705,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
   }
 
   override def do_>>(that: Int)(implicit sourceInfo: SourceInfo): UInt = {
-    if (Builder.legacyShiftRightWidth) legacyShiftRight(that)
+    if (Builder.useLegacyWidth) legacyShiftRight(that)
     else binop(sourceInfo, UInt(this.width.unsignedShiftRight(that)), ShiftRightOp, validateShiftAmount(that))
   }
   override def do_>>(that: BigInt)(implicit sourceInfo: SourceInfo): UInt =
@@ -811,12 +811,8 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
 
   override private[chisel3] def _asUIntImpl(first: Boolean)(implicit sourceInfo: SourceInfo): UInt = this
 
-  private[chisel3] override def connectFromBits(
-    that: Bits
-  )(
-    implicit sourceInfo: SourceInfo
-  ): Unit = {
-    this := that.asUInt
+  override private[chisel3] def _fromUInt(that: UInt)(implicit sourceInfo: SourceInfo): this.type = {
+    _resizeToWidth(that, this.widthOption)(identity).asInstanceOf[this.type]
   }
 
   private def subtractAsSInt(that: UInt)(implicit sourceInfo: SourceInfo): SInt =
@@ -1045,7 +1041,7 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
   override def do_>>(that: Int)(implicit sourceInfo: SourceInfo): SInt = {
     // We don't need to pad to emulate old behavior for SInt, just emulate old Chisel behavior with reported width.
     // FIRRTL will give a minimum of 1 bit for SInt.
-    val newWidth = if (Builder.legacyShiftRightWidth) this.width.shiftRight(that) else this.width.signedShiftRight(that)
+    val newWidth = if (Builder.useLegacyWidth) this.width.shiftRight(that) else this.width.signedShiftRight(that)
     binop(sourceInfo, SInt(newWidth), ShiftRightOp, validateShiftAmount(that))
   }
   override def do_>>(that: BigInt)(implicit sourceInfo: SourceInfo): SInt =
@@ -1071,13 +1067,8 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
 
   override def do_asSInt(implicit sourceInfo: SourceInfo): SInt = this
 
-  private[chisel3] override def connectFromBits(
-    that: Bits
-  )(
-    implicit sourceInfo: SourceInfo
-  ): Unit = {
-    this := that.asSInt
-  }
+  override private[chisel3] def _fromUInt(that: UInt)(implicit sourceInfo: SourceInfo): this.type =
+    _resizeToWidth(that.asSInt, this.widthOption)(_.asSInt).asInstanceOf[this.type]
 }
 
 sealed trait Reset extends Element with ToBoolable {
@@ -1118,12 +1109,10 @@ final class ResetType(private[chisel3] val width: Width = Width(1)) extends Elem
     DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)
   )
 
-  private[chisel3] override def connectFromBits(
-    that: Bits
-  )(
-    implicit sourceInfo: SourceInfo
-  ): Unit = {
-    this := that
+  override private[chisel3] def _fromUInt(that: UInt)(implicit sourceInfo: SourceInfo): Data = {
+    val _wire = Wire(this.cloneTypeFull)
+    _wire := that
+    _wire
   }
 
   /** @group SourceInfoTransformMacro */
@@ -1162,14 +1151,7 @@ sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends El
     DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)
   )
 
-  // TODO Is this right?
-  private[chisel3] override def connectFromBits(
-    that: Bits
-  )(
-    implicit sourceInfo: SourceInfo
-  ): Unit = {
-    this := that.asBool.asAsyncReset
-  }
+  override private[chisel3] def _fromUInt(that: UInt)(implicit sourceInfo: SourceInfo): Data = that.asBool.asAsyncReset
 
   /** @group SourceInfoTransformMacro */
   def do_asAsyncReset(implicit sourceInfo: SourceInfo): AsyncReset = this
@@ -1299,4 +1281,8 @@ sealed class Bool() extends UInt(1.W) with Reset {
   /** @group SourceInfoTransformMacro */
   def do_asAsyncReset(implicit sourceInfo: SourceInfo): AsyncReset =
     pushOp(DefPrim(sourceInfo, AsyncReset(), AsAsyncResetOp, ref))
+
+  override private[chisel3] def _fromUInt(that: UInt)(implicit sourceInfo: SourceInfo): this.type = {
+    _resizeToWidth(that, this.widthOption)(identity).asBool.asInstanceOf[this.type]
+  }
 }