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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.6k 652

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.7k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.8k 272

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.3k 374

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 927 236

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 748 180

Repositories

Showing 10 of 112 repositories
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog’s past year of commit activity
    C++ 448 Apache-2.0 77 47 (2 issues need help) 0 Updated Feb 22, 2026
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 8 6 0 0 Updated Feb 22, 2026
  • UHDM Public

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/UHDM’s past year of commit activity
    C++ 250 Apache-2.0 42 14 0 Updated Feb 22, 2026
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,585 Apache-2.0 652 350 (1 issue needs help) 145 Updated Feb 21, 2026
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 44 Apache-2.0 23 17 3 Updated Feb 21, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    SystemVerilog 41 766 0 0 Updated Feb 21, 2026
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 38 Apache-2.0 36 72 9 Updated Feb 21, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 141 Apache-2.0 89 220 (12 issues need help) 90 Updated Feb 21, 2026
  • caliptra-cfi Public

    Code-flow Integrity module to mitigate glitches and fault injections

    chipsalliance/caliptra-cfi’s past year of commit activity
    Rust 2 Apache-2.0 4 3 0 Updated Feb 21, 2026
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 22 Apache-2.0 42 131 (6 issues need help) 24 Updated Feb 21, 2026
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