@@ -166,7 +166,7 @@ class TypeAnnotationMemSpec extends AnyFunSpec with Matchers with chiselTests.Ut
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}
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}
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- describe(" Memory annotations with MPORT connections" ) {
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+ describe(" Memory Annotations with MPORT connections" ) {
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val targetDir = os.pwd / " test_run_dir" / " TywavesAnnotationSpec" / " Memories Annotations with MPORT connections"
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val args : Array [String ] = Array (" --target" , " chirrtl" , " --target-dir" , targetDir.toString)
@@ -205,7 +205,7 @@ class TypeAnnotationMemSpec extends AnyFunSpec with Matchers with chiselTests.Ut
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}
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}
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- describe(" Memory annotations with MPORT connections of complex types" ) {
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+ describe(" Memory Annotations with MPORT connections of complex types" ) {
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import circtTests .tywavesTests .TywavesAnnotationCircuits .DataTypesCircuits .MyBundle
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val targetDir =
@@ -270,4 +270,100 @@ class TypeAnnotationMemSpec extends AnyFunSpec with Matchers with chiselTests.Ut
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checkAnno(expectedMatches, os.read(targetDir / " TopCircuitMem.fir" ))
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}
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}
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+
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+ describe(" Masked Memories Annotations" ) {
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+ val targetDir =
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+ os.pwd / " test_run_dir" / " TywavesAnnotationSpec" / " Masked Memories Annotations"
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+ val args : Array [String ] = Array (" --target" , " chirrtl" , " --target-dir" , targetDir.toString)
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+
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+ it(" should annotate a SyncMem with mask" ) {
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+ val mSize = 100
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+ new ChiselStage (true )
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+ .execute(
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+ args,
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+ Seq (ChiselGeneratorAnnotation (() => new TopCircuitMemWithMask (SInt (7 .W ), classOf [SyncReadMem [SInt ]], mSize)))
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+ )
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+ val expectedMatches = Seq (
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+ (
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+ createExpected(
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+ " ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>mem" ,
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+ s " SInt<7> \\ [ $mSize\\ ] \\ [4 \\ ] " ,
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+ " SyncReadMem"
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+ ),
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+ 1
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+ ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>mask" , s " Bool \\ [ $mSize\\ ] " , " Wire" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>mask\\ [0\\ ]" , " Bool" , " Wire" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>idx" , " UInt<2>" , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>in" , s " SInt<7> \\ [ $mSize\\ ] " , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>in\\ [0\\ ]" , " SInt<7>" , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>out" , s " SInt<7> \\ [ $mSize\\ ] " , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>out\\ [0\\ ]" , " SInt<7>" , " IO" ), 1 ),
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+ // tmp wire generated in syncreadmem
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>_WIRE" , " UInt<2>" , " Wire" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT" , s " SInt<7> \\ [ $mSize\\ ] " , " MemPort" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT\\ [0\\ ]" , " SInt<7>" , " MemPort" ), 1 ),
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+ (
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+ createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT_1" , s " SInt<7> \\ [ $mSize\\ ] " , " MemPort" ),
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+ 1
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+ ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT_1\\ [0\\ ]" , " SInt<7>" , " MemPort" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>clock" , " Clock" , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>reset" , " Bool" , " IO" ), 1 )
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+ )
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+ checkAnno(expectedMatches, os.read(targetDir / " TopCircuitMemWithMask.fir" ))
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+ }
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+
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+ it(" should annotate a Mem with mask" ) {
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+ val mSize = 100
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+ new ChiselStage (true )
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+ .execute(
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+ args,
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+ Seq (ChiselGeneratorAnnotation (() => new TopCircuitMemWithMask (SInt (7 .W ), classOf [Mem [SInt ]], mSize)))
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+ )
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+ val expectedMatches = Seq (
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>mem" , s " SInt<7> \\ [ $mSize\\ ] \\ [4 \\ ] " , " Mem" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>mask" , s " Bool \\ [ $mSize\\ ] " , " Wire" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>mask\\ [0\\ ]" , " Bool" , " Wire" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>idx" , " UInt<2>" , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>in" , s " SInt<7> \\ [ $mSize\\ ] " , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>in\\ [0\\ ]" , " SInt<7>" , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>out" , s " SInt<7> \\ [ $mSize\\ ] " , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>out\\ [0\\ ]" , " SInt<7>" , " IO" ), 1 ),
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+ // tmp wire generated in syncreadmem
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT" , s " SInt<7> \\ [ $mSize\\ ] " , " MemPort" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT\\ [0\\ ]" , " SInt<7>" , " MemPort" ), 1 ),
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+ (
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+ createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT_1" , s " SInt<7> \\ [ $mSize\\ ] " , " MemPort" ),
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+ 1
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+ ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>MPORT_1\\ [0\\ ]" , " SInt<7>" , " MemPort" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>clock" , " Clock" , " IO" ), 1 ),
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+ (createExpected(" ~TopCircuitMemWithMask\\ |TopCircuitMemWithMask>reset" , " Bool" , " IO" ), 1 )
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+ )
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+ checkAnno(expectedMatches, os.read(targetDir / " TopCircuitMemWithMask.fir" ))
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+ }
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+
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+ it(" should annotate an SRAM with mask" ) {
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+ val cName = " TopCircuitSRAMWithMask"
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+ new ChiselStage (true )
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+ .execute(
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+ args,
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+ Seq (ChiselGeneratorAnnotation (() => new TopCircuitSRAMWithMask (SInt (7 .W ))))
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+ )
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+ val expectedMatches = Seq (
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+ (createExpected(s " ~ $cName\\ | $cName>mem_sram " , " SInt<7>\\ [2\\ ]\\ [4\\ ]" , " SramTarget" ), 1 ),
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+ (createExpected(s " ~ $cName\\ | $cName>mem.writePorts \\ [0 \\ ].mask " , s " Bool \\ [2 \\ ] " , " Wire" ), 1 ),
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+ (createExpected(s " ~ $cName\\ | $cName>mem.writePorts \\ [0 \\ ].mask \\ [0 \\ ] " , " Bool" , " Wire" ), 1 ),
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+ // Since the inner type is a vector
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+ (createExpected(s " ~ $cName\\ | $cName>mem.readPorts \\ [0 \\ ].data \\ [0 \\ ] " , " SInt<7>" , " Wire" ), 1 ),
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+ (createExpected(s " ~ $cName\\ | $cName>mem.writePorts \\ [0 \\ ].data \\ [0 \\ ] " , " SInt<7>" , " Wire" ), 1 ),
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+ (createExpected(s " ~ $cName\\ | $cName>clock " , " Clock" , " IO" ), 1 ),
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+ (createExpected(s " ~ $cName\\ | $cName>reset " , " Bool" , " IO" ), 1 )
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+ ) ++ createExpectedSRAMs(s " ~ $cName\\ | $cName>mem " , 4 , " SInt<7>\\ [2\\ ]" , 1 , 1 , 0 )
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+
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+ checkAnno(expectedMatches, os.read(targetDir / s " $cName.fir " ))
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+
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+ }
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+ }
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}
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