Skip to content

Commit 69e9c76

Browse files
committed
Annotate primitive definitions (i.e. tmp results) also outside when/otherwise
1 parent c289be6 commit 69e9c76

File tree

1 file changed

+5
-3
lines changed

1 file changed

+5
-3
lines changed

core/src/main/scala/chisel3/tywavesinternal/TywavesAnnotation.scala

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -141,16 +141,18 @@ object TywavesChiselAnnotation {
141141
// }) //++ createAnno(chisel3.Wire(innerType))
142142
}
143143
command match {
144-
case e: DefPrim[_] => Seq.empty // TODO: check prim
144+
case e: DefPrim[_] => createAnno(e.id)
145145
case e @ DefWire(info, id) => createAnno(id)
146146
case e @ DefReg(info, id, clock) => createAnno(id)
147147
case e @ DefRegInit(info, id, clock, reset, init) => createAnno(id)
148148
case e @ DefMemory(info, id, t, size) => createAnnoMem(id, id.getClass.getSimpleName, size, t)
149149
case e @ DefSeqMemory(info, id, t, size, ruw) => createAnnoMem(id, id.getClass.getSimpleName, size, t)
150150
case e @ FirrtlMemory(info, id, t, size, readPortNames, writePortNames, readwritePortNames) =>
151151
createAnnoMem(id, id.getClass.getSimpleName, size, t)
152-
case e @ DefMemPort(info, id, source, dir, idx, clock) => Seq.empty //createAnno(id)
153-
case Connect(info, loc, exp) => createAnno(exp)
152+
// Annotating DefMemPort causes errors in firtool, firtool does not support annotating DefMemPort
153+
case e @ DefMemPort(info, id, source, dir, idx, clock) => Seq.empty //createAnno(id)
154+
// Connect should not be annotated. I used, it would annotate also tmp expressions that are not declared
155+
case Connect(info, loc, exp) => Seq.empty
154156
case PropAssign(info, loc, exp) => Seq.empty
155157
case Attach(info, locs) => Seq.empty
156158
case DefInvalid(info, arg) => Seq.empty // TODO: check invalid

0 commit comments

Comments
 (0)