@@ -141,16 +141,18 @@ object TywavesChiselAnnotation {
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// }) //++ createAnno(chisel3.Wire(innerType))
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}
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command match {
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- case e : DefPrim [_] => Seq .empty // TODO: check prim
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+ case e : DefPrim [_] => createAnno(e.id)
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case e @ DefWire (info, id) => createAnno(id)
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case e @ DefReg (info, id, clock) => createAnno(id)
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case e @ DefRegInit (info, id, clock, reset, init) => createAnno(id)
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case e @ DefMemory (info, id, t, size) => createAnnoMem(id, id.getClass.getSimpleName, size, t)
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case e @ DefSeqMemory (info, id, t, size, ruw) => createAnnoMem(id, id.getClass.getSimpleName, size, t)
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case e @ FirrtlMemory (info, id, t, size, readPortNames, writePortNames, readwritePortNames) =>
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createAnnoMem(id, id.getClass.getSimpleName, size, t)
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- case e @ DefMemPort (info, id, source, dir, idx, clock) => Seq .empty // createAnno(id)
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- case Connect (info, loc, exp) => createAnno(exp)
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+ // Annotating DefMemPort causes errors in firtool, firtool does not support annotating DefMemPort
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+ case e @ DefMemPort (info, id, source, dir, idx, clock) => Seq .empty // createAnno(id)
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+ // Connect should not be annotated. I used, it would annotate also tmp expressions that are not declared
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+ case Connect (info, loc, exp) => Seq .empty
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case PropAssign (info, loc, exp) => Seq .empty
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case Attach (info, locs) => Seq .empty
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case DefInvalid (info, arg) => Seq .empty // TODO: check invalid
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