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Fix test circuits
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src/test/scala/circtTests/tywavesTests/TywavesAnnotationCircuits.scala

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,10 @@ object TywavesAnnotationCircuits {
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}
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// Circuit using intrinsics
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class ExampleIntrinsicModule(str: String) extends IntrinsicModule("OtherIntrinsic", Map("STRING" -> str)) {}
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class ExampleIntrinsicModule(str: String) extends IntrinsicModule("OtherIntrinsic", Map("STRING" -> str)) {
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val b = IO(Input(Bool()))
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val bout = IO(Output(Bool()))
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}
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class TopCircuitIntrinsic extends RawModule {
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val myIntrinsicModule1: ExampleIntrinsicModule = Module(new ExampleIntrinsicModule("Hello"))
@@ -350,6 +353,7 @@ object TywavesAnnotationCircuits {
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val topBundle = IO(Input(new TopBundle(Bool(), "hello", 'c', true, otherBundle.cloneType)))
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val caseClassBundle = IO(Input(CaseClassExample(1, new OtherBundle(UInt(2.W), baseBundle.cloneType))))
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val anonBundle = IO(Input(new Bundle {}))
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}
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