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Haskell to VHDL/Verilog/SystemVerilog compiler
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Jun 29, 2024 - Haskell
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Jun 27, 2024 - Python
RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Jun 7, 2024 - SystemVerilog
32-bit Superscalar RISC-V CPU
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Sep 18, 2021 - Verilog
Digital Signature Service : creation, extension and validation of advanced electronic signatures
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Jun 6, 2024 - Java
VUnit is a unit testing framework for VHDL/SystemVerilog
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Jun 27, 2024 - VHDL
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
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Feb 3, 2024
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
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Nov 29, 2020 - VHDL
Open source machine learning accelerators
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Mar 24, 2024 - Scala
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
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Feb 8, 2023 - Verilog
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
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Jun 29, 2024 - C
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