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Pull requests: alexforencich/verilog-ethernet

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Pull requests list

Update axis_xgmii_tx_64.v
#227 opened Oct 4, 2024 by drewranck Loading…
remove IODDR_STYLE from ssio_sdr_in instantiation in ssio_sdr_in_diff
#214 opened Jul 18, 2024 by lmbollen Loading…
1
Add VC707 board example
#198 opened Mar 8, 2024 by jrrk2 Loading…
Header_mem overflow
#195 opened Feb 23, 2024 by renardo18 Loading…
Add example design for KCU105
#171 opened Oct 17, 2023 by mkravch Loading…
Add devcontainer environment for the repo
#151 opened Mar 10, 2023 by vmayoral Loading…
1
Add license need to ZCU102 reference design
#147 opened Feb 14, 2023 by vmayoral Loading…
5
Add Digilent Genesys2 RGMII example
#144 opened Feb 7, 2023 by viktor-prutyanov Loading…
1
Fix #124 by converting to integer
#134 opened Oct 5, 2022 by david-sawatzke Loading…
1
Add Xilinx Kintex UltraScale+ KCU116 board
#96 opened Oct 11, 2021 by lschuermann Loading…
Example for Digilent Genesys2 board (XC7K325T)
#93 opened Sep 16, 2021 by unbtorsten Loading…
Fix udp checksum header overflow
#84 opened Jun 18, 2021 by hannodewind Loading…
Added STLV7325 board
#77 opened May 7, 2021 by aignacio Loading…
3
fix overflow in parameter sizes for ARP timeouts
#75 opened Apr 15, 2021 by AaronCleaver Loading…
2
Add Xilinx VC709 example
#62 opened Jan 4, 2021 by wingel Loading…
Minor fixes and improvements
#27 opened Mar 16, 2020 by Reisswolf Loading…
ARP: resolve IP multicast
#18 opened Jan 9, 2020 by sergachev Loading…
3
A complete Quartus Prime 17.1 project (Windows)
#14 opened Jul 5, 2019 by briansune Loading…
Genesys2
#6 opened Jan 16, 2019 by jrrk Loading…
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