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107 Open 64 Closed
107 Open 64 Closed
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Issues list

Can you add a module to support SPI to MII conversion, like the chip DM9051
#239 opened Dec 20, 2024 by woodyuni
1
PTP_CLOCK
#235 opened Dec 12, 2024 by Unicorn619
Adding additional Platform support
#234 opened Nov 14, 2024 by jpalmer904
Deembedded Blockdesign Arty A7 Echo-Server
#233 opened Oct 28, 2024 by Felolie
1
ExaNIC_X10 problem
#230 opened Oct 16, 2024 by andylgh
export to ku060
#229 opened Oct 7, 2024 by andylgh
6
No rule to make target
#228 opened Oct 4, 2024 by pitpg
1
Wrong bit with on 10G MAC Tx start_packet_reg
#226 opened Oct 4, 2024 by drewranck
multiple UDP stream support
#225 opened Sep 27, 2024 by lizajoseph
Error run make project for KC705 board
#222 opened Aug 31, 2024 by saman-coder
1
Defining the ethernet frame in verilog testbench
#220 opened Aug 21, 2024 by casager
4
I dream of one day seeing fq_codel (rfc8290) deeply embedded in an ethernet switch
#219 opened Aug 14, 2024 by dtaht
Eth
#216 opened Jul 25, 2024 by Tiaan1991
Link to Icarus Verilog in Readme returns Error 404
#213 opened Jul 14, 2024 by cube1us
Translate data from AXI to ethernet
#211 opened Jun 26, 2024 by thocaptain
Bug in udp_checksum_gen
#206 opened Apr 25, 2024 by SebastianSchelle
SGMII design in Stratix 10 using Gx bank
#205 opened Apr 24, 2024 by fpgapsyc
6
Jumbo Frame Support - Not Working
#204 opened Apr 24, 2024 by abu7770
2
test_ip_eth_tx_64.py hangs
#203 opened Apr 19, 2024 by EdwinEstep
4
How to download and install Icarus Verilog in linux environment?
#202 opened Apr 16, 2024 by lizajoseph
2
Is there a block diagram available for the UDP echo server design ?
#201 opened Apr 1, 2024 by lizajoseph
How to simulate and test the verilog-ethernet design?
#197 opened Mar 4, 2024 by lizajoseph
6
Can this design be validated on Alveo u50 card ?
#196 opened Feb 26, 2024 by lizajoseph
9
How To Trigger ARP Mechanism?
#194 opened Feb 23, 2024 by yunusesergun
2
UDP flow
#191 opened Feb 8, 2024 by anushkaASB
1
ProTip! no:milestone will show everything without a milestone.