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@JacyCui JacyCui commented Aug 18, 2025

Hello,

First of all, thank you for maintaining this excellent project — it’s been a great resource for understanding and working with Ethernet designs in Verilog.

While reading through rtl/eth_demux.v, I noticed that the first assignment to s_eth_hdr_ready_next is immediately overwritten by the second one, so it appears to be redundant.

if (!frame_reg && s_eth_hdr_valid && s_eth_hdr_ready) begin
    // start of frame, grab select value
    select_ctl = select;
    drop_ctl = drop;
    frame_ctl = 1'b1;

    select_next = select_ctl;
    drop_next = drop_ctl;
    frame_next = frame_ctl;

    s_eth_hdr_ready_next = 1'b0; // duplicated

    m_eth_hdr_valid_next = (!drop_ctl) << select_ctl;
    m_eth_dest_mac_next = s_eth_dest_mac;
    m_eth_src_mac_next = s_eth_src_mac;
    m_eth_type_next = s_eth_type;
end

s_eth_hdr_ready_next = !frame_next && !m_eth_hdr_valid_next; // fully overrides the previous assignment

This pull request removes the duplicated line for clarity and readability, without affecting functionality. This is a very small cleanup. Thanks again for your work on this project!

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