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export to ku060 #229
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i change the eth_xcvr_gt.tcl as follow: set preset {GTH-10GBASE-R} set freerun_freq {125} set config [dict create] dict set config TX_LINE_RATE $line_rate proc create_gtwizard_ip {name preset config} { variant with channel and commondict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] create_gtwizard_ip "${base_name}_full" $preset $config variant with channel onlydict set config ENABLE_OPTIONAL_PORTS $extra_ports create_gtwizard_ip "${base_name}_channel" $preset $config |
xdc file as follow: #100M #set_property -dict {PACKAGE_PIN E22 IOSTANDARD DIFF_SSTL12} [get_ports clk_100m_p] set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVDS} [get_ports clk_100m_p] set_property -dict {PACKAGE_PIN AP9 IOSTANDARD LVCMOS33} [get_ports {leds[0]}] #REF_CLK #SFP_A set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS33} [get_ports {sfp_a_tx_dis}] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] create_clock -period 6.400 -name sfp_a_refclk_p -waveform {0.000 3.200} [get_ports sfp_a_refclk_p] 161.1328125 MHz MGT reference clock#create_clock -period 6.206 -name sfp_a_refclk_p [get_ports sfp_a_refclk_p] |
the status : phy_rx_block_lock = 1 and sfp_qpll0lock =1 this normal but eth is no link, Is it incorrect where the port was transplanted? As far as I understand it, gth ref clk is give correct and gth pin assign ok |
The rx_status signal is more reliable than rx_block_lock, so look at that one. Do you see rx_status high when connected to an external 10G NIC? Do you see rx_status high when you use a loopback SFP? |
Does rx_status refer to the following signal?
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By |
I referenced the ExaNIC_X10 project and ported it to my own Ku060 board. Now, I have a problem where I downloaded the program to the board but the network card is not connected. The top-level is as follows:
module udp_stack_10g #
(
parameter C_S_AXI_ADDR_WIDTH = 8,
parameter C_S_AXI_DATA_WIDTH = 32,
)(
// AXI4_LITE
// System Signals
input wire clk, // 156.25Mhz
input wire reset_n,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire s_axi_awvalid,
output wire s_axi_awready,
);
//******************************************************************************
// 内部信号定义
//******************************************************************************
wire [4:0] cmd_phy_addr;
wire [4:0] cmd_reg_addr;
wire [15:0] cmd_data;
wire [1:0] cmd_opcode;
wire cmd_start; // pulse
wire [15:0] phy_rdata;
wire [7:0] prescale;
wire mdio_busy;
endmodule
`resetall
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