-
Notifications
You must be signed in to change notification settings - Fork 710
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
test_ip_eth_tx_64.py
hangs
#203
Comments
Hi, Could you let me know, how to run the simulation for this design. I have installed "cocotb", "cocotbext-axi, cocotbext-eth, and Icarus Verilog (version 10.3), however when I run make WAVES=1 in this path "verilog-ethernet/example/Alveo/fpga_25g/tb/fpga_core" I get following error /usr/local/bin/vvp -M /home/[email protected]/anaconda3/lib/python3.9/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp -fst -fst Traceback (most recent call last): |
It looks like you need to install |
Thank you very much, I am able to run the simulation tests after installing scapy |
Glad to hear it! |
After the latest commit to
ip_eth_tx_64.v
(9b5a8cf24aeeeee9d0eadabb3136f7e7722544e2
), the MyHDL testbench hangs indefinitely:The only changes I made were to tell the testbench where to find the myhdl VPI bindings. Here's a sample of the log output:
Note that this doesn't happen before that commit. Also note that the 8-bit version does not hang, completing in about 16seconds on my machine:
The text was updated successfully, but these errors were encountered: