XiangShan (香山) is an open-source high-performance RISC-V processor project.
中文说明在此。
Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.
Copyright 2020-2022 by Peng Cheng Laboratory.
XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.
- Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io
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The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this branch, which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the main branch. Present version of Nanhu is V3.
The micro-architecture overview of Nanhu-V3 (南湖V3) is shown below.
Some of the key directories are shown below.
.
├── src
│ └── main/scala # design files
│ ├── device # virtual device for simulation
│ ├── system # SoC wrapper
│ ├── top # top module
│ ├── utils # utilization code
│ ├── xiangshan # main design code
│ └── xstransforms # some useful firrtl transforms
├── scripts # scripts for agile development
├── fudian # floating unit submodule of XiangShan
├── huancun # L2/L3 cache submodule of XiangShan
├── difftest # difftest co-simulation framework
└── ready-to-run # pre-built simulation images
make bsp
make idea
- Run
make verilogto generate verilog code. The output file isbuild/XSTop.v. - Refer to
Makefilefor more information.
- Set environment variable
NEMU_HOMEto the absolute path of the NEMU project. - Set environment variable
NOOP_HOMEto the absolute path of the XiangShan project. - Set environment variable
AM_HOMEto the absolute path of the AM project. - Install
mill. Refer to the Manual section in this guide. - Clone this project and run
make initto initialize submodules.
- Install Verilator, the open-source Verilog simulator.
- Run
make emu_rtlto build the C++ simulator./sim/emu/comp/emuwith Verilator. - Refer to
./sim/emu/comp/emu --helpfor run-time arguments of the simulator. - Refer to
Makefileandverilator.mkfor more information.
Example:
make emu_rtl -j32
make emu_rtl-run RUN_BIN=coremark-3-iteration.binIn the development of XiangShan, some components from the open-source community are employed. All relevant usage is listed below.
| Sub-module | Source | Detail |
|---|---|---|
| L2 Cache/LLC | Sifive block-inclusivecache | Our new L2/L3 design are inspired by Sifive's block-inclusivecache. |
| Diplomacy/TileLink | Rocket-chip | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
| Vector Function Unit | riscv-vector | We reused vector function units in Intel's VPU |
We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the license.