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[SCR] Update release scripts (#108)
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Siudya committed Jul 22, 2024
1 parent c24ae6c commit 90256ca
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Showing 11 changed files with 201 additions and 63 deletions.
3 changes: 2 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -364,4 +364,5 @@ sim
!ready-to-run/*

novas*
verdiLog/
verdiLog/
Nanhu-Release-*
51 changes: 15 additions & 36 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ SIM_TOP = $(PREFIX)SimTop
FPGATOP = top.TopMain
BUILD_DIR ?= ./build

TOP_V = $(BUILD_DIR)/$(TOP).sv
TOP_V = $(BUILD_DIR)/rtl/$(TOP).sv
SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).sv

SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
Expand Down Expand Up @@ -91,29 +91,20 @@ update-vmem-path:
src/main/resources/TLROT/src/lowrisc_systems_rot_top_0.1/rtl/rot_top.sv
@echo "Change ROT vmem init file to $(ROT_VMEM_DIR)"

POST_COMP_OPTS = $(BUILD_DIR) $(ARG_PREFIX)
ifdef VCS
POST_COMP_OPTS += --vcs
endif
ifdef PACK
POST_COMP_OPTS += --pack-release
endif

$(TOP_V): $(SCALA_FILE) update-vmem-path
mkdir -p $(@D)
time -o $(@D)/time.log mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \
mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \
--config $(CONFIG) --full-stacktrace --num-cores $(NUM_CORES) \
$(RELEASE_ARGS) --target systemverilog | tee build/make.log
ifeq ($(VCS), 1)
@sed -i $$'s/$$fatal/assert(1\'b0)/g' $@
else
@sed -i 's/$$fatal/xs_assert(`__LINE__)/g' $@
endif
@python3 scripts/assertion_alter.py -o $@ $@
@sed -i "s/assign \([a-zA-Z0-9_]\+\) = .* ? \(.*\) : [0-9]\+'bx;/assign \1 = \2;/g" $@
@sed -i 's/_LOG_MODULE_PATH_/%m/g' $@
@sed -i 's/\(\b[a-zA-Z_0-9]\+_[0-9]\+x[0-9]\+\b\)/$(PREFIX)\1/g' $@
@sed -i '/\/\/ ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----/,$$d' $@
@sed -i -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_bits_/m_\1_\2_/g' \
-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_bits_/s_\1_\2_/g' $@
@sed -i -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_/m_\1_\2_/g' \
-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_\(ready\|valid\)/s_\1_\2_\3/g' $@
@sed -i -e '/^ .*DummyDPICWrapper/i\`ifndef SYNTHESIS' \
-e '/^ .*DummyDPICWrapper/{:a N; /;/!ba s/;/;\n`endif/ };' $@
@sed -i -E -e '/^ .*Delayer(_[0-9]*)? difftest/i\`ifndef SYNTHESIS' \
-e '/^ .*Delayer(_[0-9]*)? difftest/{:a N; /;/!ba s/;/;\n`endif/ };' $@
$(RELEASE_ARGS) --target systemverilog --split-verilog
@python3 scripts/postcompile/postcompile.py $(POST_COMP_OPTS)

verilog: $(TOP_V)

Expand All @@ -132,25 +123,13 @@ endif
--config $(CONFIG) --full-stacktrace --num-cores $(NUM_CORES) \
$(SIM_ARGS) --target systemverilog | tee build/make.log
ifeq ($(VCS), 1)
@sed -i $$'s/$$fatal/assert(1\'b0)/g' $@
@sed -i -E -f scripts/postcompile/vcs.sed $@
else ifeq ($(PLDM),1)
@sed -i -e 's/$$fatal/$$finish/g' $@
else
@sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $@
@sed -i -E -f scripts/postcompile/verilator.sed $@
endif
@python3 scripts/assertion_alter.py -o $@ $@
@sed -i "s/assign \([a-zA-Z0-9_]\+\) = .* ? \(.*\) : [0-9]\+'bx;/assign \1 = \2;/g" $@
@sed -i 's/_LOG_MODULE_PATH_/%m/g' $@
@sed -i 's/\(\b[a-zA-Z_0-9]\+_[0-9]\+x[0-9]\+\b\)/$(PREFIX)\1/g' $@
@sed -i '/\/\/ ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----/,$$d' $@
@sed -i -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_bits_/m_\1_\2_/g' \
-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_bits_/s_\1_\2_/g' $@
@sed -i -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_/m_\1_\2_/g' \
-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_\(ready\|valid\)/s_\1_\2_\3/g' $@
@sed -i -e '/^ .*DummyDPICWrapper/i\`ifndef SYNTHESIS' \
-e '/^ .*DummyDPICWrapper/{:a N; /;/!ba s/;/;\n`endif/ };' $@
@sed -i -E -e '/^ .*Delayer(_[0-9]*)? difftest/i\`ifndef SYNTHESIS' \
-e '/^ .*Delayer(_[0-9]*)? difftest/{:a N; /;/!ba s/;/;\n`endif/ };' $@
@python3 scripts/postcompile/assertion_alter.py -o $@ $@

FILELIST := $(ABS_WORK_DIR)/build/cpu_flist.f

Expand Down
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
import os
import argparse
import re
import queue
from queue import Queue

def match(line, pattern_c):
res = pattern_c.search(line.strip())
Expand All @@ -15,12 +15,15 @@ def gen_spaces(str):
first_letter = str.lstrip()[0]
return str[0:str.find(first_letter)-2:1]

def alter_print_info(file_queue):
rex_assert_begin = re.compile("\$error\(")
rex_assert_body = re.compile("Assertion failed")
rex_assert_end = re.compile("\);")
assertion_queue = queue.Queue()
res_queue = queue.Queue()
rex_assert_begin = re.compile("\$error\(")
rex_assert_body = re.compile("Assertion failed")
rex_assert_end = re.compile("\);")

def alter_print_info(file_queue:Queue[str]):
if(file_queue.empty()):
return Queue[str]()
assertion_queue = Queue()
res_queue = Queue()

while(True):
line = file_queue.get()
Expand All @@ -30,19 +33,19 @@ def alter_print_info(file_queue):
res_queue.put(gen_spaces(line) + "begin\n")
if(is_single_line):
res_queue.put(gen_prefix(line) + "$fwrite(32'h80000002, \"Assertion failed: %m @ %t\", $time);\n")
line = line.replace("Assertion failed:", "").replace("$error(", "$fwrite(32'h80000002, ")
line = line.replace("Assertion failed", "").replace("$error(", "$fwrite(32'h80000002, ")
res_queue.put(line)
res_queue.put(gen_spaces(line) + "end\n")
else:
if(match(line, rex_assert_body)):
line = line.replace("$error(", "$fwrite(32'h80000002, ").replace("Assertion failed:", "")
line = line.replace("$error(", "$fwrite(32'h80000002, ").replace("Assertion failed", "")
else:
line = line.replace("$error(", "$fwrite(32'h80000002, ")
assertion_queue.put(line)
while(True):
line = file_queue.get()
if(match(line, rex_assert_body)):
line = line.replace("Assertion failed:", "")
line = line.replace("Assertion failed", "")
assertion_queue.put(line)
if(match(line, rex_assert_end)):
ol = assertion_queue.get()
Expand Down Expand Up @@ -82,7 +85,7 @@ def print_queue(filename, line_queue):
print("Input file not exsist!")
os._exit()

file_queue = queue.Queue()
file_queue = Queue()
with open(file_path,"r") as f:
file_lines = f.readlines()
for line in file_lines:
Expand Down
114 changes: 114 additions & 0 deletions scripts/postcompile/postcompile.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,114 @@
import argparse
import os
import queue
import re
from assertion_alter import alter_print_info, print_queue
from functools import reduce
import concurrent.futures
from tqdm import tqdm
from datetime import date
import shutil

macro_pat = [
re.compile(r".*sram_array_\dp\d+x\d+m\d+.*"),
re.compile(r".*ClockGate(_\d*)?\.(v|sv)")
]

def macro_match(line:str) -> bool:
hitVec = [(p.match(line) is not None) for p in macro_pat]
return reduce(lambda a, b: a or b, hitVec)

def get_files(build_path:str) -> list[str]:
files = list[str]()
for f in os.scandir(build_path):
file_path = os.path.join(build_path, f.path)
if f.is_file() and (f.path.endswith(".sv") or f.path.endswith(".v")):
files.append(file_path)
elif f.is_dir():
files += get_files(file_path)
return files

this_dir = os.path.dirname(os.path.abspath(__file__))
cmd = "sed -i -E -f {} {}"

class RtlFile:
file = ""
vcs_style = True
scr = ""

def run(self):
run_cmd = cmd.format(self.scr, self.file)
os.system(run_cmd)

buf = queue.Queue[str]()
with open(self.file, "r") as f:
file_lines = f.readlines()
if(len(file_lines) == 0):
print("{} failed!".format(self.file))
exit()
for line in file_lines:
buf.put(line)
q = alter_print_info(buf)
print_queue(self.file, q)

def __init__(self, file:str, vcs:bool):
self.file = file
if(vcs):
self.scr = os.path.join(this_dir, "vcs.sed")
else:
self.scr = os.path.join(this_dir, "verilator.sed")

if __name__ == "__main__":
parser = argparse.ArgumentParser(description='Post Compilation Script for XS')
parser.add_argument('build', type=str, help='Build diretory')
parser.add_argument('--vcs', action='store_true', help='VCS style assertion')
parser.add_argument('-j', '--jobs', default=16, type=int, help='Parallel jobs', metavar='')
parser.add_argument('--pack-release', action='store_true', help='Release all artifacts')
parser.add_argument('--prefix', type=str, default="", help='Prefix for release')
args = parser.parse_args()
curdir = os.path.abspath(os.curdir)
build_dir = os.path.join(curdir, args.build)
release_base = f'{args.prefix}Nanhu-Release-{date.today().strftime("%b-%d-%Y")}'
release_dir = os.path.join(curdir, release_base)
pack = args.pack_release
vcs = args.vcs
jobs = args.jobs
workerList = []

for item in get_files(build_dir):
workerList.append(RtlFile(item, vcs))

print("Doing post-compiling procedures!")
with concurrent.futures.ThreadPoolExecutor(jobs) as executor:
results = concurrent.futures.as_completed([executor.submit(lambda x: x.run(), w) for w in workerList])
list(tqdm(results, total=len(workerList)))

if(pack):
print(f"Making release package at {release_dir}!")
if(os.path.exists(release_dir)):
shutil.rmtree(release_dir)
shutil.copytree(build_dir, release_dir)
macros_dir = os.path.join(release_dir, "macros")
top_flist = os.path.join(release_dir, "top.f")
macros_flist = os.path.join(release_dir, "macros.f")
os.makedirs(macros_dir)

tf = open(top_flist, "w")
mf = open(macros_flist, "w")
tf.write("-f $release_dir/macros.f\n")
for fn in get_files(release_dir):
bn = os.path.basename(fn)
if(macro_match(bn)):
shutil.move(fn, os.path.join(macros_dir, bn))
mf.write(f"$release_dir/macros/{bn}\n")
else:
tf.write(fn.replace(release_dir, "$release_dir") + "\n")
tf.close()
mf.close()

gzfile = f"{release_base}.tar.gz!"
if(os.path.exists(gzfile)):
os.remove(gzfile)
print(f"Packing {gzfile}!")
pack_cmd = f"tar -zcf {release_base}.tar.gz {release_base}"
os.system(pack_cmd)
11 changes: 11 additions & 0 deletions scripts/postcompile/vcs.sed
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
s/\$fatal/assert(1'b0)/g
s/assign ([a-zA-Z0-9_]+) = .* \? (.*) : [0-9]+'bx;/assign \1 = \2;/g
s/_LOG_MODULE_PATH_/%m/g
s/(peripheral|memory)_0_(aw|ar|w|r|b)_bits_/m_\1_\2_/g
s/(dma)_0_(aw|ar|w|r|b)_bits_/s_\1_\2_/g
s/(peripheral|memory)_0_(aw|ar|w|r|b)_/m_\1_\2_/g
s/(dma)_0_(aw|ar|w|r|b)_(ready|valid)/s_\1_\2_\3/g
/^ .*DummyDPICWrapper/i\`ifndef SYNTHESIS
/^ .*DummyDPICWrapper/{:L0; N; /;/!b L0; s/;/;\n`endif/ };
/^ .*Delayer(_[0-9]*)? difftest/i\`ifndef SYNTHESIS
/^ .*Delayer(_[0-9]*)? difftest/{:L1; N; /;/!b L1; s/;/;\n`endif/ };
11 changes: 11 additions & 0 deletions scripts/postcompile/verilator.sed
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
s/\$fatal/xs_assert(`__LINE__)/g
s/assign ([a-zA-Z0-9_]+) = .* \? (.*) : [0-9]+'bx;/assign \1 = \2;/g
s/_LOG_MODULE_PATH_/%m/g
s/(peripheral|memory)_0_(aw|ar|w|r|b)_bits_/m_\1_\2_/g
s/(dma)_0_(aw|ar|w|r|b)_bits_/s_\1_\2_/g
s/(peripheral|memory)_0_(aw|ar|w|r|b)_/m_\1_\2_/g
s/(dma)_0_(aw|ar|w|r|b)_(ready|valid)/s_\1_\2_\3/g
/^ .*DummyDPICWrapper/i\`ifndef SYNTHESIS
/^ .*DummyDPICWrapper/{:L0; N; /;/!b L0; s/;/;\n`endif/ };
/^ .*Delayer(_[0-9]*)? difftest/i\`ifndef SYNTHESIS
/^ .*Delayer(_[0-9]*)? difftest/{:L1; N; /;/!b L1; s/;/;\n`endif/ };
19 changes: 14 additions & 5 deletions src/main/scala/top/Top.scala
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@
package top

import chisel3._
import chisel3.experimental.{ChiselAnnotation, annotate}
import xiangshan._
import utils._
import system._
Expand All @@ -29,6 +30,7 @@ import freechips.rocketchip.jtag.JTAGIO
import xs.utils.{DFTResetSignals, FileRegisters, ResetGen}
import xs.utils.sram.SramBroadcastBundle
import huancun.{HCCacheParamsKey, HuanCun}
import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
import xs.utils.mbist.{MbistInterface, MbistPipeline}
import xs.utils.perf.DebugOptionsKey

Expand Down Expand Up @@ -124,10 +126,17 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter {
lazy val module = new Impl

class Impl extends LazyRawModuleImp(this) {
FileRegisters.add("dts", dts)
FileRegisters.add("graphml", graphML)
FileRegisters.add("json", json)
FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
FileRegisters.add("misc", "dts", dts)
FileRegisters.add("misc", "graphml", graphML)
FileRegisters.add("misc", "json", json)
FileRegisters.add("misc", "plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
private val prefix = p(PrefixKey)
if(prefix != "") {
val mod = this.toNamed
annotate(new ChiselAnnotation {
def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
})
}

val dma = IO(Flipped(misc.dma.cloneType))
val peripheral = IO(misc.peripheral.cloneType)
Expand Down Expand Up @@ -302,7 +311,7 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter {

object TopMain extends App {
val (config, firrtlOpts) = ArgParser.parse(args)
xsphase.PrefixHelper.prefix = config(PrefixKey)
xs.utils.GlobalData.prefix = config(PrefixKey)
val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
(new XiangShanStage).execute(firrtlOpts, Seq(
FirtoolOption("-O=release"),
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/top/XiangShanStage.scala
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ class XiangShanStage extends Stage {
Dependency[chisel3.stage.phases.MaybeAspectPhase],
Dependency[chisel3.stage.phases.AddSerializationAnnotations],
Dependency[chisel3.stage.phases.Convert],
Dependency[xsphase.Prefix],
Dependency[xstransform.DedupTile],
Dependency[chisel3.stage.phases.MaybeInjectingPhase],
Dependency[circt.stage.phases.AddImplicitOutputFile],
Dependency[circt.stage.phases.Checks],
Expand Down
Original file line number Diff line number Diff line change
@@ -1,22 +1,21 @@
package xsphase
package xstransform
import firrtl.AnnotationSeq
import firrtl.annotations._
import firrtl.ir._
import firrtl.options.Phase
import firrtl.renamemap.MutableRenameMap
import firrtl.stage.FirrtlCircuitAnnotation

object PrefixHelper {
object DedupHelper {
val coreNamePat = "XSTile_?[0-9]+"
var prefix = "bosc_"
def StatementsWalker(stmt:Statement):Statement = {
stmt match {
case s: DefInstance =>{
if(s.module.matches(coreNamePat)){
println(s"Rename ${s.module} calling to XSTile!")
s.copy(module = prefix + "XSTile")
s.copy(module = "XSTile")
} else {
s.copy(module = prefix + s.module)
s
}
}
case s: Conditionally => s.copy(conseq = StatementsWalker(s.conseq), alt = StatementsWalker(s.alt))
Expand All @@ -29,20 +28,20 @@ object PrefixHelper {
}
}

class Prefix extends Phase {
class DedupTile extends Phase {
override def prerequisites: Seq[Nothing] = Seq.empty
override def optionalPrerequisites: Seq[Nothing] = Seq.empty
override def optionalPrerequisiteOf: Seq[Nothing] = Seq.empty
override def invalidates(a: Phase) = false
private val prefix = PrefixHelper.prefix
private val prefix = ""
private val renameMap = MutableRenameMap()
def transform(annotations: AnnotationSeq): AnnotationSeq = {
val prefixedAS = annotations.flatMap {
case a: FirrtlCircuitAnnotation =>
val mods = a.circuit.modules.map {
case mm@Module(_, name, _, body) => {
renameMap.record(ModuleTarget(a.circuit.main, name), ModuleTarget(prefix + a.circuit.main, prefix + name))
val nst = PrefixHelper.StatementsWalker(body)
val nst = DedupHelper.StatementsWalker(body)
mm.copy(name = prefix + name, body = nst)
}
case em@ExtModule(_, name, _, defname, _) => {
Expand Down
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