Chisel switch to version 6.1.0 (#85)

Siudya · Feb 26, 2024 · 129ac4d · 129ac4d
1 parent dc49884
commit 129ac4d
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Showing 27 changed files with 44 additions and 43 deletions.
diff --git a/build.sc b/build.sc
@@ -24,8 +24,8 @@ import $file.`rocket-chip`.cde.common
 import $file.`rocket-chip`.hardfloat.build
 
 val defaultVersions = Map(
-  "chisel" -> "6.0.0-M3",
-  "chisel-plugin" -> "6.0.0-M3",
+  "chisel" -> "6.1.0",
+  "chisel-plugin" -> "6.1.0",
   "chiseltest" -> "5.0.0",
   "scala" -> "2.13.10",
   "scalatest" -> "3.2.7"

diff --git a/coupledL2 b/coupledL2
diff --git a/difftest b/difftest
diff --git a/fudian b/fudian
diff --git a/huancun b/huancun
diff --git a/rocket-chip b/rocket-chip
diff --git a/src/main/scala/xiangshan/backend/execute/exu/ExuNodes.scala b/src/main/scala/xiangshan/backend/execute/exu/ExuNodes.scala
@@ -19,7 +19,7 @@
  ****************************************************************************************/
 package xiangshan.backend.execute.exu
 import org.chipsalliance.cde.config.Parameters
-import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.SourceInfo
 import chisel3.util._
 import freechips.rocketchip.diplomacy._
 import xiangshan.ExuOutput

diff --git a/src/main/scala/xiangshan/backend/execute/exublock/ExuBlockNodes.scala b/src/main/scala/xiangshan/backend/execute/exublock/ExuBlockNodes.scala
@@ -20,7 +20,7 @@
 package xiangshan.backend.execute.exublock
 
 import org.chipsalliance.cde.config.Parameters
-import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.SourceInfo
 import xiangshan.backend.execute.exu.ExuConfig
 import xiangshan.backend.execute.exucx.{ExuComplexParam, ExuComplexWritebackNode}
 import freechips.rocketchip.diplomacy.{AdapterNode, RenderedEdge, SimpleNodeImp, SinkNode, ValName}

diff --git a/src/main/scala/xiangshan/backend/execute/exucx/ExuComplexNodes.scala b/src/main/scala/xiangshan/backend/execute/exucx/ExuComplexNodes.scala
@@ -19,7 +19,7 @@
  ****************************************************************************************/
 package xiangshan.backend.execute.exucx
 import org.chipsalliance.cde.config.Parameters
-import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.SourceInfo
 import freechips.rocketchip.diplomacy._
 import xiangshan.backend.execute.exu.{ExuConfig, ExuOutwardImpl, ExuType}
 import xiangshan.backend.issue.{IssueBundle, RsParam}

diff --git a/src/main/scala/xiangshan/backend/execute/fu/csr/Trigger.scala b/src/main/scala/xiangshan/backend/execute/fu/csr/Trigger.scala
@@ -240,7 +240,7 @@ trait SdtrigExt {
     val eq = data === tdata
     val ge = data >= tdata
     val lt = data < tdata
-    val res = MuxLookup(matchType, false.B, Seq(
+    val res = MuxLookup(matchType, false.B)(Seq(
       TrigMatchEnum.EQ -> eq,
       TrigMatchEnum.GE -> ge,
       TrigMatchEnum.LT -> lt

diff --git a/src/main/scala/xiangshan/backend/execute/fu/mdu/Multiplier.scala b/src/main/scala/xiangshan/backend/execute/fu/mdu/Multiplier.scala
@@ -75,7 +75,7 @@ class ArrayMulDataModule(len: Int) extends Module {
   var last_x = WireInit(0.U(3.W))
   for(i <- Range(0, len, 2)){
     val x = if(i==0) Cat(a(1,0), 0.U(1.W)) else if(i+1==len) SignExt(a(i, i-1), 3) else a(i+1, i-1)
-    val pp_temp = MuxLookup(x, 0.U, Seq(
+    val pp_temp = MuxLookup(x, 0.U)(Seq(
       1.U -> b_sext,
       2.U -> b_sext,
       3.U -> bx2,
@@ -84,7 +84,7 @@ class ArrayMulDataModule(len: Int) extends Module {
       6.U -> neg_b
     ))
     val s = pp_temp(len)
-    val t = MuxLookup(last_x, 0.U(2.W), Seq(
+    val t = MuxLookup(last_x, 0.U(2.W))(Seq(
       4.U -> 2.U(2.W),
       5.U -> 1.U(2.W),
       6.U -> 1.U(2.W)

diff --git a/src/main/scala/xiangshan/backend/execute/fu/mdu/SRT16Divider.scala b/src/main/scala/xiangshan/backend/execute/fu/mdu/SRT16Divider.scala
@@ -173,7 +173,7 @@ class SRT16DividerDataModule(len: Int) extends Module {
   val rCarryInit = 0.U(itn_len.W)
 
   val rSumInitTrunc = Cat(0.U(1.W), rSumInit(itn_len - 4, itn_len - 4 - 4 + 1)) // 0.00___
-  val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W),
+  val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W))(
     Array(
       0.U -> "b00100".U(5.W),
       1.U -> "b00100".U(5.W),
@@ -185,7 +185,7 @@ class SRT16DividerDataModule(len: Int) extends Module {
       7.U -> "b01000".U(5.W),
     )
   )
-  val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W),
+  val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W))(
     Array(
       0.U -> "b01100".U(5.W),
       1.U -> "b01110".U(5.W),
@@ -239,10 +239,10 @@ class SRT16DividerDataModule(len: Int) extends Module {
 
   // Give values to the regs and wires above...
   val dForLookup = dPos(len-2, len-4)
-  mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6)
-    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6)
-    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)),
-    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(3)), 11) ,0.U(1.W))
+  mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6)
+    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6)
+    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)),
+    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(3)), 11) ,0.U(1.W))
   )
   udNeg := VecInit( Cat(SignExt(dPos, 66), 0.U(2.W)),
     Cat(SignExt(dPos, 67), 0.U(1.W)),

diff --git a/src/main/scala/xiangshan/backend/execute/fu/mdu/SRT4Divider.scala b/src/main/scala/xiangshan/backend/execute/fu/mdu/SRT4Divider.scala
@@ -180,7 +180,7 @@ class SRT4DividerDataModule(len: Int) extends Module {
 
   // obtaining 1st quotient
   val rSumInitTrunc = Cat(0.U(1.W), rSumInit(itn_len - 4, itn_len - 4 - 4 + 1)) // 0.00___
-  val mInitPos1 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b00100".U(5.W),
+  val mInitPos1 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b00100".U(5.W))(
     Array(
       0.U -> "b00100".U(5.W),
       1.U -> "b00100".U(5.W),
@@ -192,7 +192,7 @@ class SRT4DividerDataModule(len: Int) extends Module {
       7.U -> "b01000".U(5.W),
     )
   )
-  val mInitPos2 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b01100".U(5.W),
+  val mInitPos2 = MuxLookup(dNormAbsReg(len - 2, len - 2 - 3 + 1), "b01100".U(5.W))(
     Array(
       0.U -> "b01100".U(5.W),
       1.U -> "b01110".U(5.W),
@@ -409,7 +409,7 @@ class SRT4QDS(len: Int, itn_len: Int) extends Module {
         csa1.io.in(1) := trunc25(remCarryX16)
         csa2.io.in(2) := trunc25(dXq)
       }
-      csa1.io.in(2) := MuxLookup(dForLookup, "b0000000".U, mLookUpTable.minus_m(i))
+      csa1.io.in(2) := MuxLookup(dForLookup, "b0000000".U)(mLookUpTable.minus_m(i))
       csa2.io.in(0) := csa1.io.out(0)
       csa2.io.in(1) := csa1.io.out(1)(5, 0) << 1
       (csa2.io.out(0) + (csa2.io.out(1)(5, 0) << 1))(6)

diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStationNodes.scala b/src/main/scala/xiangshan/backend/issue/ReservationStationNodes.scala
@@ -22,7 +22,7 @@ import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
-import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.SourceInfo
 import xiangshan.MicroOp
 import xiangshan.backend.execute.exucx.ExuComplexParam
 

diff --git a/src/main/scala/xiangshan/backend/regfile/RegfileNodes.scala b/src/main/scala/xiangshan/backend/regfile/RegfileNodes.scala
@@ -22,7 +22,7 @@ package xiangshan.backend.regfile
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy.{MixedNexusNode, _}
 import chisel3._
-import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.SourceInfo
 import xiangshan.backend.execute.exucx.ExuComplexParam
 import xiangshan.backend.issue.{IssueBundle, RsParam}
 

diff --git a/src/main/scala/xiangshan/backend/writeback/WriteBackNetworkNodes.scala b/src/main/scala/xiangshan/backend/writeback/WriteBackNetworkNodes.scala
@@ -21,7 +21,7 @@ package xiangshan.backend.writeback
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import chisel3._
-import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.SourceInfo
 import chisel3.util._
 import xiangshan.ExuOutput
 import xiangshan.backend.execute.exu.{ExuConfig, ExuType}

diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
@@ -510,7 +510,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
 
   def missCohGen(cmd: UInt, param: UInt, dirty: Bool) = {
     val c = categorize(cmd)
-    MuxLookup(Cat(c, param, dirty), Nothing, Seq(
+    MuxLookup(Cat(c, param, dirty), Nothing)(Seq(
       //(effect param) -> (next)
       Cat(rd, toB, false.B)  -> Branch,
       Cat(rd, toB, true.B)   -> Branch,

diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
@@ -481,7 +481,7 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
   refill.id := req.id
   def missCohGen(cmd: UInt, param: UInt, dirty: Bool) = {
     val c = categorize(cmd)
-    MuxLookup(Cat(c, param, dirty), Nothing, Seq(
+    MuxLookup(Cat(c, param, dirty), Nothing)(Seq(
       //(effect param) -> (next)
       Cat(rd, toB, false.B)  -> Branch,
       Cat(rd, toB, true.B)   -> Branch,

diff --git a/src/main/scala/xiangshan/cache/mmu/L2TLB.scala b/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
@@ -371,7 +371,7 @@ class PTWImp(outer: PTW)(implicit p: Parameters) extends PtwModule(outer) with H
   }
 
   def outReady(source: UInt, port: Int): Bool = {
-    MuxLookup(source, true.B,
+    MuxLookup(source, true.B)(
       (0 until PtwWidth).map(i => i.U -> outArb(i).in(port).ready))
   }
 

diff --git a/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala b/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
@@ -237,7 +237,7 @@ class TlbEntry(pageNormal: Boolean, pageSuper: Boolean)(implicit p: Parameters)
     this.tag := {if (pageNormal) item.entry.tag else item.entry.tag(vpnLen-1, vpnnLen)}
     this.asid := asid
     val inner_level = item.entry.level.getOrElse(0.U)
-    this.level.map(_ := { if (pageNormal && pageSuper) MuxLookup(inner_level, 0.U, Seq(
+    this.level.map(_ := { if (pageNormal && pageSuper) MuxLookup(inner_level, 0.U)(Seq(
                                                         0.U -> 3.U,
                                                         1.U -> 1.U,
                                                         2.U -> 0.U ))

diff --git a/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala b/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala
@@ -16,7 +16,8 @@
 
 package xiangshan.mem
 
-import chisel3.experimental.{DataMirror, requireIsChiselType}
+import chisel3.experimental.requireIsChiselType
+import chisel3.reflect.DataMirror
 import chisel3._
 import chisel3.util._
 

diff --git a/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/div/SRT16Divider.scala b/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/div/SRT16Divider.scala
@@ -172,7 +172,7 @@ class SRT16DividerDataModule(len: Int) extends Module {
   val rCarryInit = 0.U(itn_len.W)
 
   val rSumInitTrunc = Cat(0.U(1.W), rSumInit(itn_len - 4, itn_len - 4 - 4 + 1)) // 0.00___
-  val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W),
+  val mInitPos1 = MuxLookup(dNormReg(len-2, len-4), "b00100".U(5.W))(
     Array(
       0.U -> "b00100".U(5.W),
       1.U -> "b00100".U(5.W),
@@ -184,7 +184,7 @@ class SRT16DividerDataModule(len: Int) extends Module {
       7.U -> "b01000".U(5.W),
     )
   )
-  val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W),
+  val mInitPos2 = MuxLookup(dNormReg(len-2, len-4), "b01100".U(5.W))(
     Array(
       0.U -> "b01100".U(5.W),
       1.U -> "b01110".U(5.W),
@@ -238,10 +238,10 @@ class SRT16DividerDataModule(len: Int) extends Module {
 
   // Give values to the regs and wires above...
   val dForLookup = dPos(len-2, len-4)
-  mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6)
-    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6)
-    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)),
-    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W), mLookUpTable2.minus_m(3)), 11) ,0.U(1.W))
+  mNeg := VecInit(Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(0)), 11), 0.U(1.W)), // (2, 5) -> (6, 6)
+    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(1)), 10) ,0.U(2.W)), // (3, 4) -> (6, 6)
+    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(2)), 10) ,0.U(2.W)),
+    Cat(SignExt(MuxLookup(dNormReg(len-2, len-4), "b00000000".U(7.W))(mLookUpTable2.minus_m(3)), 11) ,0.U(1.W))
   )
   udNeg := VecInit( Cat(SignExt(dPos, 66), 0.U(2.W)),
     Cat(SignExt(dPos, 67), 0.U(1.W)),

diff --git a/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/div/VIntDiv.scala b/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/div/VIntDiv.scala
@@ -44,7 +44,7 @@ class VIntSRT16TimeplexDivider(implicit p: Parameters) extends Module {
     busy := false.B
   }
   io.in.ready := !busy
-  val uopsTotal = MuxLookup(vsew, 0.U, Seq(
+  val uopsTotal = MuxLookup(vsew, 0.U)(Seq(
     0.U -> 8.U,
     1.U -> 4.U,
     2.U -> 2.U,

diff --git a/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/fp/VFCVT.scala b/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/fp/VFCVT.scala
@@ -2,7 +2,7 @@ package darecreek.exu.vfu.fp
 
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
-import chisel3.experimental.ChiselEnum
+import chisel3.ChiselEnum
 import chisel3.util._
 
 

diff --git a/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/fp/VFFMA.scala b/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/fp/VFFMA.scala
@@ -16,7 +16,7 @@ package darecreek.exu.vfu.fp
   * See the Mulan PSL v2 for more details.
   * ************************************************************************************* */
 
-import chisel3.experimental.ChiselEnum
+import chisel3.ChiselEnum
 import chisel3.util._
 import chisel3._
 import org.chipsalliance.cde.config._

diff --git a/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/fp/VFRec.scala b/src/main/scala/xiangshan/vector/vbackend/vexecute/vfu/fp/VFRec.scala
@@ -219,8 +219,8 @@ class VFRecDataModule(implicit val p: Parameters) extends VFPUPipelineModule {
 
 object RsqrtLookup {
   def apply(exp0: Bool, sig:UInt) = {
-    val even = MuxLookup(sig, 0.U, table(0))
-    val odd = MuxLookup(sig, 0.U, table(1))
+    val even = MuxLookup(sig, 0.U)(table(0))
+    val odd = MuxLookup(sig, 0.U)(table(1))
     Mux(exp0, odd, even)
   }
   val table = Seq(
@@ -364,7 +364,7 @@ object RsqrtLookup {
 object RecLookup {
   def apply(sig:UInt) = {
     require(sig.getWidth == 7)
-    MuxLookup(sig, 0.U, table)
+    MuxLookup(sig, 0.U)(table)
   }
   val table = Seq(
     0.U(7.W) -> 127.U(7.W),

diff --git a/xs-utils b/xs-utils
+1 −1		AXItoTL
+2 −2		build.sc
+3 −4		src/main/scala/coupledL2/MSHR.scala
+1 −1		src/main/scala/coupledL2/MainPipe.scala
+7 −7		src/main/scala/coupledL2/prefetch/sppDev2.scala
+6 −7		src/main/scala/coupledL3/MSHR.scala
+2 −2		src/main/scala/coupledL3/MainPipe.scala
+4 −4		src/main/scala/fudian/FDIV.scala
+1 −1		src/main/scala/fudian/RoundingUnit.scala
+2 −2		src/main/scala/fudian/utils/Multiplier.scala
+2 −2		build.sc
+7 −9		src/main/scala/huancun/inclusive/MSHR.scala
+5 −5		src/main/scala/huancun/noninclusive/MSHR.scala
+1 −1		docs/src/diplomacy/adder_tutorial.md
+3 −2		src/main/scala/diplomacy/BundleBridge.scala
+1 −2		src/main/scala/diplomacy/LazyModule.scala
+4 −7		src/main/scala/groundtest/TraceGen.scala
+1 −1		src/main/scala/jtag/JtagShifter.scala
+1 −1		src/main/scala/rocket/BTB.scala
+1 −1		src/main/scala/rocket/DCache.scala
+1 −1		src/main/scala/rocket/NBDcache.scala
+2 −2		src/main/scala/rocket/RocketCore.scala
+3 −3		src/main/scala/rocket/ScratchpadSlavePort.scala
+1 −1		src/main/scala/tilelink/AtomicAutomata.scala
+3 −4		src/main/scala/tilelink/Edges.scala
+1 −1		src/main/scala/tilelink/Fragmenter.scala
+2 −2		src/main/scala/tilelink/Fuzzer.scala
+2 −2		src/main/scala/tilelink/Metadata.scala
+2 −2		src/main/scala/util/RecordMap.scala
+1 −1		src/main/scala/util/TraceCoreInterface.scala
+1 −1		src/main/scala/LookupTree.scala
+2 −1		src/main/scala/MIMOQueue.scala