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Fit to chisel5
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Siudya committed Sep 19, 2023
1 parent 9f71934 commit 253c027
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15 changes: 11 additions & 4 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,26 +1,33 @@
[submodule "rocket-chip"]
path = rocket-chip
url = https://github.com/OpenXiangShan/rocket-chip.git
url = https://github.com/Siudya/rocket-chip
[submodule "difftest"]
path = difftest
url = https://github.com/Siudya/difftest.git
branch = nanhu-v3
url = https://github.com/OpenXiangShan/difftest
branch = nh3
[submodule "ready-to-run"]
path = ready-to-run
url = https://github.com/Siudya/ready-to-run
[submodule "huancun"]
path = huancun
url = https://github.com/Siudya/Huancun
url = https://github.com/Siudya/huancun
branch = chisel5
[submodule "fudian"]
path = fudian
url = https://github.com/Siudya/fudian
branch = chisel5
[submodule "xs-utils"]
path = xs-utils
url = https://github.com/Siudya/xs-utils
branch = chisel5
[submodule "utility"]
path = utility
url = https://github.com/OpenXiangShan/utility
[submodule "CoupledL2"]
path = CoupledL2
url = https://github.com/cyril0124/CoupledL2
branch = integrate_cpl2_cpl3
[submodule "coupledL2"]
path = coupledL2
url = https://github.com/cyril0124/CoupledL2
branch = chisel5
2 changes: 1 addition & 1 deletion .mill-version
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@@ -1 +1 @@
0.9.8
0.11.2
1 change: 0 additions & 1 deletion CoupledL2
Submodule CoupledL2 deleted from 0a14ad
8 changes: 6 additions & 2 deletions Makefile
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Expand Up @@ -156,16 +156,20 @@ clean:

init:
git submodule update --init
cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat
cd rocket-chip && git submodule update --init cde hardfloat

bump:
git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"

comp:
mill -i XiangShan.compile
mill -i XiangShan.test.compile

bsp:
mill -i mill.bsp.BSP/install

idea:
mill -i mill.scalalib.GenIdea/idea
mill -i mill.idea.GenIdea/idea

# verilator simulation
emu:
Expand Down
222 changes: 105 additions & 117 deletions build.sc
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Expand Up @@ -14,192 +14,180 @@
* See the Mulan PSL v2 for more details.
***************************************************************************************/

import os.Path
import mill._
import scalalib._
import scalafmt._
import os.Path
import publish._
import coursier.maven.MavenRepository
import $file.`rocket-chip`.common
import $file.`rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build
import $file.`rocket-chip`.cde.common
import $file.`rocket-chip`.hardfloat.build

object ivys {
val sv = "2.12.13"
val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.5"
val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.5"
val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.5.5"
val scalatest = ivy"org.scalatest::scalatest:3.2.2"
val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
val defaultVersions = Map(
"chisel" -> "5.0.0",
"chisel-plugin" -> "5.0.0",
"chiseltest" -> "5.0.0",
"scala" -> "2.13.10",
"scalatest" -> "3.2.7"
)

def getVersion(dep: String, org: String = "org.chipsalliance", cross: Boolean = false) = {
val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep))
if (cross)
ivy"$org:::$dep:$version"
else
ivy"$org::$dep:$version"
}

trait XSModule extends ScalaModule with PublishModule {
trait CommonModule extends ScalaModule {
override def scalaVersion = defaultVersions("scala")

override def scalacPluginIvyDeps = Agg(getVersion("chisel-plugin", cross = true))

// override this to use chisel from source
def chiselOpt: Option[PublishModule] = None
override def scalacOptions = super.scalacOptions() ++ Agg("-Ytasty-reader", "-Ymacro-annotations")

override def scalaVersion = ivys.sv
}

override def compileIvyDeps = Agg(ivys.macroParadise)
object rocketchip extends RocketChip

override def scalacPluginIvyDeps = Agg(ivys.macroParadise, ivys.chisel3Plugin)
trait RocketChip
extends millbuild.`rocket-chip`.common.RocketChipModule
with SbtModule {
def scalaVersion: T[String] = T(defaultVersions("scala"))

override def scalacOptions = Seq("-Xsource:2.11")
override def millSourcePath = os.pwd / "rocket-chip"

override def ivyDeps = if(chiselOpt.isEmpty) Agg(ivys.chisel3) else Agg.empty[Dep]
def chiselModule = None

override def moduleDeps = Seq() ++ chiselOpt
def chiselPluginJar = None

def publishVersion = "0.0.1"
def chiselIvy = Some(getVersion("chisel"))

// TODO: fix this
def pomSettings = PomSettings(
description = "XiangShan",
organization = "",
url = "https://github.com/OpenXiangShan/XiangShan",
licenses = Seq(License.`Apache-2.0`),
versionControl = VersionControl.github("OpenXiangShan", "XiangShan"),
developers = Seq.empty
)
}
def chiselPluginIvy = Some(getVersion("chisel-plugin", cross=true))

object rocketchip extends `rocket-chip`.common.CommonRocketChip {
def macrosModule = macros

val rcPath = os.pwd / "rocket-chip"
def hardfloatModule = hardfloat

override def scalaVersion = ivys.sv
def cdeModule = cde

override def scalacOptions = Seq("-Xsource:2.11")
def mainargsIvy = ivy"com.lihaoyi::mainargs:0.5.0"

override def millSourcePath = rcPath
def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.5"

object configRocket extends `rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule {
override def millSourcePath = rcPath / "api-config-chipsalliance" / "design" / "craft"
object macros extends Macros

override def scalaVersion = T {
rocketchip.scalaVersion()
}
trait Macros
extends millbuild.`rocket-chip`.common.MacrosModule
with SbtModule {

override def pomSettings = T {
rocketchip.pomSettings()
}
def scalaVersion: T[String] = T(defaultVersions("scala"))

override def publishVersion = T {
rocketchip.publishVersion()
}
def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${defaultVersions("scala")}"
}

object hardfloatRocket extends `rocket-chip`.hardfloat.build.hardfloat {
override def millSourcePath = rcPath / "hardfloat"
object hardfloat extends Hardfloat

override def scalaVersion = T {
rocketchip.scalaVersion()
}
trait Hardfloat
extends millbuild.`rocket-chip`.hardfloat.common.HardfloatModule {

def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
common.getVersion("chisel3")
) else Agg.empty[Dep]

def chisel3PluginIvyDeps = Agg(common.getVersion("chisel3-plugin", cross=true))
def scalaVersion: T[String] = T(defaultVersions("scala"))

override def millSourcePath = os.pwd / "rocket-chip" / "hardfloat" / "hardfloat"

def chiselModule = None

def chiselPluginJar = None

def chiselIvy = Some(getVersion("chisel"))

def chiselPluginIvy = Some(getVersion("chisel-plugin", cross=true))
}

def hardfloatModule = hardfloatRocket
object cde extends CDE

trait CDE
extends millbuild.`rocket-chip`.cde.common.CDEModule
with ScalaModule {

def configModule = configRocket
def scalaVersion: T[String] = T(defaultVersions("scala"))

override def millSourcePath = os.pwd / "rocket-chip" / "cde" / "cde"
}
}

object xsutils extends XSModule with SbtModule {
object difftest extends SbtModule with ScalafmtModule with CommonModule {

override def millSourcePath = os.pwd / "xs-utils"
override def ivyDeps = Agg(getVersion("chisel"))

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip
)
override def millSourcePath = os.pwd / "difftest"
}

object utility extends XSModule with SbtModule {
object fudian extends SbtModule with ScalafmtModule with CommonModule {

override def ivyDeps = Agg(getVersion("chisel"))

override def millSourcePath = os.pwd / "fudian"
}

object xsutils extends SbtModule with ScalafmtModule with CommonModule {

override def ivyDeps = Agg(getVersion("chisel"))

override def millSourcePath = os.pwd / "utility"
override def millSourcePath = os.pwd / "xs-utils"

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip
)
}

object huancun extends XSModule with SbtModule {
object huancun extends SbtModule with ScalafmtModule with CommonModule {

override def ivyDeps = Agg(getVersion("chisel"))

override def millSourcePath = os.pwd / "huancun"

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip,
xsutils
)
override def moduleDeps = super.moduleDeps ++ Seq(rocketchip, xsutils)
}

object CoupledL2 extends XSModule with SbtModule {
object coupledL2 extends SbtModule with ScalafmtModule with CommonModule {

override def ivyDeps = Agg(getVersion("chisel"))

override def millSourcePath = os.pwd / "CoupledL2"
override def millSourcePath = os.pwd / "coupledL2"

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip,
huancun,
xsutils,
utility
xsutils
)
}

object difftest extends XSModule with SbtModule {
override def millSourcePath = os.pwd / "difftest"
}

object fudian extends XSModule with SbtModule

// extends this trait to use XiangShan in other projects
trait CommonXiangShan extends XSModule with SbtModule { m =>
object XiangShan extends SbtModule with ScalafmtModule with CommonModule {

// module deps
def rocketModule: PublishModule
def difftestModule: PublishModule
def huancunModule: PublishModule
def coupledL2Module: PublishModule
def fudianModule: PublishModule
def xsutilsModule: PublishModule
def utilityModule: PublishModule

override def millSourcePath = os.pwd
override def millSourcePath = millOuterCtx.millSourcePath

override def forkArgs = Seq("-Xmx64G", "-Xss256m")

override def ivyDeps = super.ivyDeps() ++ Seq(ivys.chiseltest)
override def ivyDeps = super.ivyDeps() ++ Agg(
getVersion("chisel"),
getVersion("chiseltest", "edu.berkeley.cs"),
)

override def moduleDeps = super.moduleDeps ++ Seq(
rocketModule,
difftestModule,
huancunModule,
fudianModule,
xsutilsModule,
coupledL2Module,
utilityModule
rocketchip,
xsutils,
huancun,
difftest,
coupledL2,
fudian
)

object test extends Tests with TestModule.ScalaTest {

override def forkArgs = m.forkArgs

object test extends SbtModuleTests with TestModule.ScalaTest {
override def ivyDeps = super.ivyDeps() ++ Agg(
ivys.scalatest
getVersion("scalatest","org.scalatest")
)

def testFramework = "org.scalatest.tools.Framework"
}

}

object XiangShan extends CommonXiangShan {
override def rocketModule = rocketchip
override def difftestModule = difftest
override def huancunModule = huancun
override def fudianModule = fudian
override def xsutilsModule = xsutils
override def coupledL2Module = CoupledL2
override def utilityModule = utility
}
}
1 change: 1 addition & 0 deletions coupledL2
Submodule coupledL2 added at 8d1823
2 changes: 1 addition & 1 deletion difftest
2 changes: 1 addition & 1 deletion huancun
Submodule huancun updated 56 files
+1 −1 .gitmodules
+1 −1 .mill-version
+1 −4 Makefile
+70 −55 build.sc
+1 −1 rocket-chip
+3 −3 src/main/scala/huancun/BankedXbar.scala
+14 −14 src/main/scala/huancun/BaseDirectory.scala
+1 −1 src/main/scala/huancun/BaseMSHR.scala
+2 −2 src/main/scala/huancun/BaseSinkC.scala
+8 −1 src/main/scala/huancun/Common.scala
+4 −4 src/main/scala/huancun/CtrlUnit.scala
+10 −10 src/main/scala/huancun/DataStorage.scala
+6 −30 src/main/scala/huancun/HCCacheParameters.scala
+7 −7 src/main/scala/huancun/HuanCun.scala
+10 −10 src/main/scala/huancun/MSHRAlloc.scala
+5 −5 src/main/scala/huancun/RefillBuffer.scala
+20 −19 src/main/scala/huancun/RequestBuffer.scala
+9 −9 src/main/scala/huancun/SinkA.scala
+1 −1 src/main/scala/huancun/SinkB.scala
+3 −3 src/main/scala/huancun/SinkD.scala
+2 −2 src/main/scala/huancun/SinkE.scala
+4 −5 src/main/scala/huancun/Slice.scala
+5 −5 src/main/scala/huancun/SourceA.scala
+1 −1 src/main/scala/huancun/SourceB.scala
+4 −4 src/main/scala/huancun/SourceC.scala
+6 −6 src/main/scala/huancun/SourceD.scala
+1 −1 src/main/scala/huancun/SourceE.scala
+2 −2 src/main/scala/huancun/debug/DirectoryLogger.scala
+11 −11 src/main/scala/huancun/debug/TLLogger.scala
+3 −3 src/main/scala/huancun/inclusive/Directory.scala
+12 −12 src/main/scala/huancun/inclusive/MSHR.scala
+13 −13 src/main/scala/huancun/inclusive/SinkC.scala
+19 −19 src/main/scala/huancun/noninclusive/Directory.scala
+24 −22 src/main/scala/huancun/noninclusive/MSHR.scala
+4 −4 src/main/scala/huancun/noninclusive/ProbeHelper.scala
+12 −12 src/main/scala/huancun/noninclusive/SinkC.scala
+16 −16 src/main/scala/huancun/noninclusive/SliceCtrl.scala
+9 −9 src/main/scala/huancun/prefetch/BestOffsetPrefetch.scala
+1 −1 src/main/scala/huancun/prefetch/PrefetchParameters.scala
+1 −1 src/main/scala/huancun/prefetch/PrefetchReceiver.scala
+1 −1 src/main/scala/huancun/prefetch/Prefetcher.scala
+0 −85 src/main/scala/huancun/utils/FastArbiter.scala
+0 −69 src/main/scala/huancun/utils/TLClientsMerger.scala
+5 −5 src/main/scala/huancun/utils/Throttle.scala
+1 −1 src/test/scala/huancun/AllocatorTest.scala
+2 −2 src/test/scala/huancun/DSTest.scala
+3 −2 src/test/scala/huancun/ExampleSystem.scala
+13 −9 src/test/scala/huancun/FakeClient.scala
+3 −3 src/test/scala/huancun/L2Tester.scala
+1 −1 src/test/scala/huancun/TLDebugNode.scala
+24 −9 src/test/scala/huancun/TestTop.scala
+1 −1 src/test/scala/huancun/tlctest/DirConflictTester.scala
+3 −2 src/test/scala/huancun/tlctest/TLCTest.scala
+1 −1 src/test/scala/tltest/TLCAgent.scala
+20 −20 src/test/scala/tltest/TLCScalaMessage.scala
+1 −1 xs-utils
2 changes: 1 addition & 1 deletion ready-to-run
2 changes: 1 addition & 1 deletion rocket-chip
Submodule rocket-chip updated 356 files
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