Add prefix annotation

Makefile

@@ -39,6 +39,7 @@ ABS_WORK_DIR := $(shell pwd)
 RUN_BIN_DIR ?= $(ABS_WORK_DIR)/ready-to-run
 RUN_BIN ?= coremark-2-iteration
 CONSIDER_FSDB ?= 1
+PREFIX ?=
 MFC ?= 0
 
 ifdef FLASH
@@ -71,11 +72,11 @@ RELEASE_ARGS = --fpga-platform --enable-difftest
 DEBUG_ARGS   = --enable-difftest
 
 ifeq ($(VCS),1)
-RELEASE_ARGS += --emission-options disableRegisterRandomization -X sverilog --output-file $(TOP)
-DEBUG_ARGS += --emission-options disableRegisterRandomization -X sverilog --output-file $(SIM_TOP)
+RELEASE_ARGS += --emission-options disableRegisterRandomization -X sverilog --prefix $(PREFIX) --output-file $(TOP)
+DEBUG_ARGS += --emission-options disableRegisterRandomization -X sverilog --prefix $(PREFIX) --output-file $(SIM_TOP)
 else
-RELEASE_ARGS += --emission-options disableRegisterRandomization -E verilog --output-file $(TOP)
-DEBUG_ARGS += -E verilog --output-file $(SIM_TOP)
+RELEASE_ARGS += --emission-options disableRegisterRandomization -E verilog --prefix $(PREFIX) --output-file $(TOP)
+DEBUG_ARGS += -E verilog --prefix $(PREFIX) --output-file $(SIM_TOP)
 endif
 
 ifeq ($(RELEASE),1)
@@ -100,6 +101,7 @@ $(TOP_V): $(SCALA_FILE)
 	-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_\(ready\|valid\)/s_\1_\2_\3/g' $(BUILD_DIR)/tmp.v > $(BUILD_DIR)/tmp1.v
 	rm $@ $(BUILD_DIR)/tmp.v
 	mv $(BUILD_DIR)/tmp1.v $@
+	python3 scripts/assertion_alter.py -o $(TOP_V) $(TOP_V)
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__
 	@sed -i 's/^/\/\// ' .__head__

scalastyle-config.xml

@@ -77,7 +77,7 @@
  </check>
  <check level="warning" class="org.scalastyle.scalariform.CyclomaticComplexityChecker" enabled="true">
   <parameters>
-   <parameter name="maximum"><![CDATA[20]]></parameter>
+   <parameter name="maximum"><![CDATA[30]]></parameter>
   </parameters>
  </check>
  <check level="warning" class="org.scalastyle.scalariform.UppercaseLChecker" enabled="true"></check>

src/main/scala/top/ArgParser.scala

@@ -36,6 +36,7 @@ object ArgParser {
       |--enable-difftest
       |--enable-log
       |--disable-perf
+      |--prefix
       |""".stripMargin
 
   def getConfigByName(confString: String): Parameters = {
@@ -89,6 +90,10 @@ object ArgParser {
           nextOption(config.alter((site, here, up) => {
             case DebugOptionsKey => up(DebugOptionsKey).copy(EnableTopDown = true)
           }), tail)
+        case "--prefix" :: confString :: tail =>
+          nextOption(config.alter((site, here, up) => {
+            case PrefixKey => confString
+          }), tail)
         case option :: tail =>
           // unknown option, maybe a firrtl option, skip
           firrtlOpts :+= option

src/main/scala/top/Configs.scala

@@ -37,7 +37,7 @@ import coupledL3._
 import xiangshan.mem.prefetch.SMSParams
 
 import darecreek.exu.fu2._
-
+case object PrefixKey extends Field[String]
 class BaseConfig(n: Int) extends Config((site, here, up) => {
   case XLen => 64
   case DebugOptionsKey => DebugOptions()
@@ -52,6 +52,7 @@ class BaseConfig(n: Int) extends Config((site, here, up) => {
   case JtagDTMKey => JtagDTMKey
   case MaxHartIdBits => 2
   case EnableJtag => true.B
+  case PrefixKey => ""
 
   case VFuParamsKey => VFuParameters()
 })

src/main/scala/top/Top.scala

@@ -26,10 +26,10 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.jtag.JTAGIO
 import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils}
-import huancun.{HCCacheParamsKey, HuanCun}
 import xs.utils.{ResetGen, DFTResetSignals}
 import xs.utils.sram.BroadCastBundle
 import coupledL3._
+import xstransforms.ModulePrefixAnnotation
 
 abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
   with BindingScope
@@ -261,6 +261,7 @@ object TopMain extends App with HasRocketChipStageUtils {
     val (config, firrtlOpts) = ArgParser.parse(args)
     val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
     XiangShanStage.execute(firrtlOpts, Seq(
+      ModulePrefixAnnotation(config(PrefixKey)),
       ChiselGeneratorAnnotation(() => {
         soc.module
       })

src/main/scala/top/XiangShanStage.scala

@@ -49,7 +49,8 @@ object XiangShanStage {
       annotations ++ Seq(
         RunFirrtlTransformAnnotation(new PrintControl),
         RunFirrtlTransformAnnotation(new PrintModuleName),
-        RunFirrtlTransformAnnotation(new RenameDesiredNames)
+        RunFirrtlTransformAnnotation(new RenameDesiredNames),
+        RunFirrtlTransformAnnotation(new AddModulePrefix)
       )
     )
   }

src/main/scala/xstransforms/AddModulePrefix.scala

@@ -0,0 +1,64 @@
+package xstransforms
+
+import firrtl._
+import firrtl.annotations.{ModuleTarget, NoTargetAnnotation}
+import firrtl.ir._
+import firrtl.options.Dependency
+import firrtl.stage.Forms
+import firrtl.stage.TransformManager.TransformDependency
+import firrtl.passes.memlib.{InferReadWrite, ReplSeqMem, GenVerilogMemBehaviorModelAnno}
+
+case class ModulePrefixAnnotation(prefix: String) extends NoTargetAnnotation
+
+class AddModulePrefix extends Transform with DependencyAPIMigration {
+
+  override def prerequisites: Seq[TransformDependency] = Seq(
+    Dependency[InferReadWrite],
+    Dependency[ReplSeqMem]
+  ) ++ Forms.LowForm
+  override def optionalPrerequisites:  Seq[TransformDependency] = Forms.LowFormOptimized
+  override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
+  override def invalidates(a: Transform): Boolean = false
+
+  override protected def execute(state: CircuitState): CircuitState = {
+    val c = state.circuit
+
+    val prefixOpt = state.annotations.collectFirst {
+      case ModulePrefixAnnotation(p) => p
+    }
+
+    if (prefixOpt.isEmpty){ return state }
+
+    val prefix = prefixOpt.get
+
+    def rename(old: String): String = prefix + old
+
+    val renameMap = RenameMap()
+
+    def onStmt(s: Statement): Statement = s match {
+      case DefInstance(info, name, module, tpe) =>
+        DefInstance(info, name, rename(module), tpe)
+      case other =>
+        other.mapStmt(onStmt)
+    }
+
+    def onModule(m: DefModule): DefModule = {
+      val newName = rename(m.name)
+      renameMap.record(
+        ModuleTarget(c.main, m.name), ModuleTarget(c.main, newName)
+      )
+      m match {
+        case mod@Module(info, name, ports, body) =>
+          mod.copy(name = newName).mapStmt(onStmt)
+        case extMod@ExtModule(info, name, ports, defname, params) =>
+          extMod.copy(name = newName, defname = newName)
+      }
+    }
+
+    val newCircuit = c.mapModule(onModule)
+    state.copy(
+      circuit = newCircuit.copy(main = rename(c.main)),
+      renames = Some(renameMap)
+    )
+  }
+}