asic

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Dec 22, 2024
Python

ultraembedded / riscv

Sponsor

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RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

pulp-platform / axi

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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Dec 19, 2024
SystemVerilog

ultraembedded / biriscv

Sponsor

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32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

riscvarchive / riscv-cores-list

Star

RISC-V Cores, SoC platforms and SoCs

asic fpga risc-v socs open-isa

Updated Mar 26, 2021

esig / dss

Star

Digital Signature Service : creation, extension and validation of advanced electronic signatures

java asic validation signature xades cades pades esignature jades

Updated Dec 24, 2024
Java

ucb-bar / gemmini

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Berkeley's Spatial Array Generator

asic accelerator dnn

Updated Dec 13, 2024
Scala

VUnit / vunit

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VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated Dec 22, 2024
VHDL

ultraembedded / cores

Sponsor

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Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

zssloth / Embedded-Neural-Network

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collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

compression asic fpga deep-learning neural-network

Updated Feb 3, 2024

VLSI-EDA / PoC

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IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany