[FIRRTL] FoldRegMems: insert new ops into same block as memory #7909
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rwy7
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seldridge
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I see utility and simplicity in this approach of relocating the register to the end. This will likely produce worse Verilog in the output unless a later pass comes and reorders things to remove the temporary wire. That said, this optimization is so rare anyway and this patch fixes a known bug re: layers.
LGTM
| // CHECK: firrtl.matchingconnect %Memory, {{%.+}} : !firrtl.uint<32> | ||
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Same review comments as last time for the test. The layer test is large. Can it be made smaller by either: (1) removing connections or (2) reducing the number of ports?
Before this PR, FoldRegMems would construct new ops in the "body of the parent FModuleOp". We need to place these ops in the same block as the memory. This PR fixes a bug where, when a memory under a layerblock was canonicalized to a register, the register would be placed at the original location of the memory (under the layerblock), but its readers would be placed outside the layerblock, resulting in a dominance checking error.
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Before this PR, FoldRegMems would construct new ops in the "body of the parent FModuleOp". We need to place these ops in the same block as the memory.
This PR fixes a bug where, when a memory under a layerblock was canonicalized to a register, the register would be placed at the original location of the memory (under the layerblock), but its readers would be placed outside the layerblock, resulting in a dominance checking error.