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733 Open 1,450 Closed
733 Open 1,450 Closed
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Issues list

[Comb] or(concat, concat) -> concat & or(and, concat) -> concat(extract) canonicalizer Comb Involving the `comb` dialect enhancement New feature or request
#8260 opened Feb 20, 2025 by maerhart
[CI] Cancelled CI saves sccache
#8258 opened Feb 20, 2025 by uenoku
[LLHD] Mem2Reg creates drives to read-only signals bug Something isn't working LLHD
#8246 opened Feb 15, 2025 by fabianschuiki
1
[LLHD] Mem2Reg crash on reasonable input bug Something isn't working LLHD
#8245 opened Feb 15, 2025 by fabianschuiki
1
1
[Arc] Flatten public modules Arc Involving the `arc` dialect bug Something isn't working
#8232 opened Feb 12, 2025 by fabianschuiki
Tests that require Z3 fail rather than being unsupported
#8231 opened Feb 12, 2025 by mikeurbach
1
[ImportVerilog] Problem with conditional + register bug Something isn't working LLHD
#8226 opened Feb 12, 2025 by felixridoux
@maerhart
2
[ESI]Assersion: dyn_cast on a non-existent value ESI
#8219 opened Feb 11, 2025 by hailongSun2000
[MooreToCore] OOB array slices of unpacked arrays lowered like packed arrays Moore
#8215 opened Feb 10, 2025 by maerhart
1
[HWToLLVM] Don't crash on OOB accesses
#8214 opened Feb 10, 2025 by maerhart
1
[arcilator] Install configuration missing for arcilator-runtime.h Arc Involving the `arc` dialect
#8212 opened Feb 10, 2025 by maerhart
[MooreToCore]Unexpected observed values in llhd.wait. Moore
#8211 opened Feb 8, 2025 by hailongSun2000
@hailongSun2000
1
[circt-bmc] Add support for verif.symbolic_value verif
#8197 opened Feb 6, 2025 by fabianschuiki
2
Documentation on Analyzing Circuits with Python Bindings
#8195 opened Feb 5, 2025 by tymcauley
1
[RTG][Elaboration] Each virtual register should only be materialized once and every user should use it bug Something isn't working RTG Involving the `rtg` dialect
#8193 opened Feb 5, 2025 by maerhart
[MooreToCore] Crash when getting values to observe Moore
#8176 opened Feb 3, 2025 by maerhart
@hailongSun2000
6
[ImportVerilog] Crash on ordering-methods-reverse test bug Something isn't working ImportVerilog
#8173 opened Feb 2, 2025 by fabianschuiki
[MooreToCore] Out-of-bounds moore.extract lowered incorrectly Moore
#8163 opened Jan 31, 2025 by maerhart
1
[FIRRTL] LowerToHW discards private modules FIRRTL Involving the `firrtl` dialect
#8153 opened Jan 30, 2025 by fabianschuiki
[circt-test] sby runner doesn't fail if module doesn't exist bug Something isn't working
#8145 opened Jan 29, 2025 by fabianschuiki
Firtool and aarch64
#8135 opened Jan 28, 2025 by timmerrifield
2
[MooreToCore] Support moore.array_create good first issue Good for newcomers Moore
#8128 opened Jan 25, 2025 by fabianschuiki
@manojks1999
1
[FIRRTL] Intrinsic documentation: Ports and Direction tables are bit confusing documentation Improvements or additions to documentation FIRRTL Involving the `firrtl` dialect
#8111 opened Jan 22, 2025 by dtzSiFive
Status and getting started
#8099 opened Jan 20, 2025 by ecstrema
2
[FIRRTL] more strict connect semantic
#8069 opened Jan 12, 2025 by sequencer
1
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