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Pull requests: llvm/circt

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231 Open 7,567 Closed
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Pull requests list

[PyCDE] Add AGENTS.md with hardware dev tips PyCDE Python CIRCT Design Entry API
#10369 opened Apr 30, 2026 by teqdruid Contributor Loading…
[OM] Add ElaborateObject pass
#10363 opened Apr 30, 2026 by uenoku Member Loading…
4
[FIRRTL] Create classes for transitive properties
#10362 opened Apr 30, 2026 by seldridge Member Loading…
7
[Support] Add parallel instance graph visitors
#10353 opened Apr 29, 2026 by seldridge Member • Draft
4
[ImportVerilog] Support use-before-declare across module bodies
#10350 opened Apr 28, 2026 by AmurG Contributor Loading…
[FIRRTL] Add class for module w/ any property
#10349 opened Apr 28, 2026 by seldridge Member Loading…
4
[FIRRTL] LowerLayers: Inline enabled layers FIRRTL Involving the `firrtl` dialect
#10348 opened Apr 28, 2026 by rwy7 Contributor Loading…
4
[Sim][MooreToCore] Lowering moore.fmt.string op to the new sim.fmt.string
#10346 opened Apr 28, 2026 by sunhailong2001 Contributor Loading…
4
[ImportVerilog] HierarchicalNames should skip reprocessing identical module instances
#10341 opened Apr 28, 2026 by rocallahan • Draft
[ImportVerilog] Capture analysis should skip reprocessing identical module instances
#10338 opened Apr 28, 2026 by rocallahan Loading…
12
fix: update flattenIndices to generate correct indices for a flattened memref
#10327 opened Apr 25, 2026 by Abhilekhgautam Loading…
1
5
[Support] Add SparseOpSCC utility
#10305 opened Apr 23, 2026 by fzi-hielscher Contributor Loading…
14
[FIRRTL] Eliminate Implicit Truncation
#10294 opened Apr 21, 2026 by darthscsi Contributor Loading…
16
[OM] Introduce explicit evaluator state and op patterns
#10265 opened Apr 18, 2026 by uenoku Member • Draft
1
14
[LowerToHW] Avoid "assert/assume/cover" string comparison, refactor label creation, NFC
#10251 opened Apr 17, 2026 by uenoku Member Loading…
Plumb dbg.variable anchors into SMT symbol names
#10237 opened Apr 16, 2026 by 5iri Contributor Loading…
6
Add union roundtrip
#10236 opened Apr 16, 2026 by jpienaar Member Loading…
2
ImportVerilog: fix signedness propagation in ConversionExpression lowering
#10235 opened Apr 16, 2026 by kaituo-crypto Loading…
7
[Synth] Make FunctionalReduction runnable on any op
#10230 opened Apr 15, 2026 by SmitVaishnav Contributor Loading…
3
[FIRRTL][LowerLayers] Add probe type support
#10223 opened Apr 15, 2026 by prithayan Contributor Loading…
1
[Sim] Add cascade erase for print/proc.print format/get_file producer chains
#10204 opened Apr 14, 2026 by nanjo712 Contributor Loading…
4
[Synth][CutRewriter] Add timing-preserving area-flow reselection
#10193 opened Apr 13, 2026 by uenoku Member • Draft
5
[SSP] Reimplement auxiliary dependences without symbols
#10189 opened Apr 12, 2026 by jopperm Contributor Loading…
1
don't emit redundant write_en = 0 for seq_mem
#10174 opened Apr 10, 2026 by Abhilekhgautam Loading…
1
2
DRAFT: [3/2] [Moore] Lower class object access and virtual dispatch through LLVM memory
#10166 opened Apr 9, 2026 by Scheremo Contributor • Draft
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