Skip to content

Commit

Permalink
fixing misc. errors in flow_tree.cc
Browse files Browse the repository at this point in the history
  • Loading branch information
karimtera committed Jul 15, 2022
1 parent e83d19f commit fa4aa99
Show file tree
Hide file tree
Showing 2 changed files with 6 additions and 8 deletions.
12 changes: 5 additions & 7 deletions verilog/analysis/flow_tree.cc
Original file line number Diff line number Diff line change
Expand Up @@ -41,10 +41,10 @@ absl::Status FlowTree::GenerateControlFlowTree() {
elses_[ifs_.back()].push_back(idx);
if (current_enum == PP_endif) {
auto& myelses = elses_[ifs_.back()];
for (int i = 0; i < myelses.size(); i++) {
for (int j = i + 1; j < myelses.size(); j++) {
if (!i && j == myelses.size() - 1) continue;
edges_[myelses[i]].push_back(myelses[j] + 1);
for (auto it = myelses.begin(); it != myelses.end(); it++) {
for (auto it2 = it + 1; it2 != myelses.end(); it2++) {
if (it == myelses.begin() && it2 == myelses.end() - 1) continue;
edges_[*it].push_back(*it2 + (it2 != myelses.end() - 1));
}
}
ifs_.pop_back();
Expand All @@ -53,15 +53,13 @@ absl::Status FlowTree::GenerateControlFlowTree() {
idx++;
}
idx = 0;
int prv_enum = 0;
for (auto u : source_sequence_) {
current_enum = u.token_enum();
if (current_enum != PP_else && current_enum != PP_elsif) {
if (idx > 0) edges_[idx - 1].push_back(idx);
} else {
if (idx > 0) edges_[idx - 1].push_back(edges_[idx].back());
}
prv_enum = current_enum;
idx++;
}

Expand All @@ -78,7 +76,7 @@ absl::Status FlowTree::DepthFirstSearch(int index) {
for (auto u : edges_[index]) {
auto status = FlowTree::DepthFirstSearch(u); // handle errors
}
if (index == source_sequence_.size() - 1) {
if (index == int(source_sequence_.size()) - 1) {
variants_.push_back(current_sequence_);
}
if (curr.token_enum() != PP_Identifier && curr.token_enum() != PP_ifndef &&
Expand Down
2 changes: 1 addition & 1 deletion verilog/tools/preprocessor/verilog_preprocessor.cc
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ static absl::Status MultipleCU(const SubcommandArgsRange& args, std::istream&,
std::string source_view{post_preproc};
verilog::VerilogAnalyzer analyzer(source_view, "file1", config);
auto analyze_status = analyzer.Analyze();
const auto& mydata = analyzer.Data().Contents();
/* const auto& mydata = analyzer.Data().Contents(); */
/* outs<<mydata; */

/* TODO(karimtera): regarding conditionals
Expand Down

0 comments on commit fa4aa99

Please sign in to comment.