Skip to content

Commit e83d19f

Browse files
karimterakarimtera
committed
applying clang-format
1 parent 0005982 commit e83d19f

File tree

3 files changed

+97
-88
lines changed

3 files changed

+97
-88
lines changed

‎verilog/analysis/flow_tree.cc‎

Lines changed: 42 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -12,51 +12,54 @@
1212
// See the License for the specific language governing permissions and
1313
// limitations under the License.
1414

15-
#include <vector>
15+
#include "verilog/analysis/flow_tree.h"
16+
1617
#include <map>
1718
#include <string>
19+
#include <vector>
20+
1821
#include "absl/status/status.h"
1922
#include "absl/strings/str_cat.h"
2023
#include "absl/strings/string_view.h"
2124
#include "common/lexer/token_stream_adapter.h"
2225
#include "verilog/parser/verilog_token_enum.h"
23-
#include "verilog/analysis/flow_tree.h"
2426

2527
namespace verilog {
2628

27-
absl::Status FlowTree::GenerateControlFlowTree(){
28-
int idx=0;
29-
int current_enum=0;
30-
for(auto u:source_sequence_){
31-
current_enum=u.token_enum();
29+
absl::Status FlowTree::GenerateControlFlowTree() {
30+
int idx = 0;
31+
int current_enum = 0;
32+
for (auto u : source_sequence_) {
33+
current_enum = u.token_enum();
3234

33-
if(current_enum == PP_ifdef || current_enum == PP_ifndef){
35+
if (current_enum == PP_ifdef || current_enum == PP_ifndef) {
3436
ifs_.push_back(idx);
3537
elses_[ifs_.back()].push_back(idx);
3638

37-
}else if(current_enum == PP_else || current_enum == PP_elsif || current_enum == PP_endif){
39+
} else if (current_enum == PP_else || current_enum == PP_elsif ||
40+
current_enum == PP_endif) {
3841
elses_[ifs_.back()].push_back(idx);
39-
if(current_enum == PP_endif){
40-
auto & myelses= elses_[ifs_.back()];
41-
for(int i=0;i<myelses.size();i++){
42-
for(int j=i+1;j<myelses.size();j++){
43-
if(!i&&j==myelses.size()-1) continue;
44-
edges_[myelses[i]].push_back(myelses[j]+1);
42+
if (current_enum == PP_endif) {
43+
auto& myelses = elses_[ifs_.back()];
44+
for (int i = 0; i < myelses.size(); i++) {
45+
for (int j = i + 1; j < myelses.size(); j++) {
46+
if (!i && j == myelses.size() - 1) continue;
47+
edges_[myelses[i]].push_back(myelses[j] + 1);
4548
}
4649
}
4750
ifs_.pop_back();
4851
}
4952
}
5053
idx++;
5154
}
52-
idx=0;
53-
int prv_enum=0;
54-
for(auto u:source_sequence_){
55-
current_enum=u.token_enum();
56-
if(current_enum != PP_else && current_enum != PP_elsif){
57-
if(idx>0) edges_[idx-1].push_back(idx);
58-
}else{
59-
if(idx>0) edges_[idx-1].push_back(edges_[idx].back());
55+
idx = 0;
56+
int prv_enum = 0;
57+
for (auto u : source_sequence_) {
58+
current_enum = u.token_enum();
59+
if (current_enum != PP_else && current_enum != PP_elsif) {
60+
if (idx > 0) edges_[idx - 1].push_back(idx);
61+
} else {
62+
if (idx > 0) edges_[idx - 1].push_back(edges_[idx].back());
6063
}
6164
prv_enum = current_enum;
6265
idx++;
@@ -65,22 +68,25 @@ absl::Status FlowTree::GenerateControlFlowTree(){
6568
return absl::OkStatus();
6669
}
6770

68-
absl::Status FlowTree::DepthFirstSearch(int index){
69-
const auto & curr=source_sequence_[index];
70-
if(curr.token_enum()!=PP_Identifier && curr.token_enum() != PP_ifndef && curr.token_enum()!=PP_ifdef
71-
&& curr.token_enum()!=PP_define && curr.token_enum()!=PP_define_body
72-
&& curr.token_enum()!=PP_elsif && curr.token_enum()!=PP_else && curr.token_enum()!=PP_endif) current_sequence_.push_back(curr);
73-
for(auto u:edges_[index]){
74-
auto status = FlowTree::DepthFirstSearch(u); // handle errors
71+
absl::Status FlowTree::DepthFirstSearch(int index) {
72+
const auto& curr = source_sequence_[index];
73+
if (curr.token_enum() != PP_Identifier && curr.token_enum() != PP_ifndef &&
74+
curr.token_enum() != PP_ifdef && curr.token_enum() != PP_define &&
75+
curr.token_enum() != PP_define_body && curr.token_enum() != PP_elsif &&
76+
curr.token_enum() != PP_else && curr.token_enum() != PP_endif)
77+
current_sequence_.push_back(curr);
78+
for (auto u : edges_[index]) {
79+
auto status = FlowTree::DepthFirstSearch(u); // handle errors
7580
}
76-
if(index==source_sequence_.size()-1){
81+
if (index == source_sequence_.size() - 1) {
7782
variants_.push_back(current_sequence_);
7883
}
79-
if(curr.token_enum()!=PP_Identifier && curr.token_enum() != PP_ifndef && curr.token_enum()!=PP_ifdef
80-
&& curr.token_enum()!=PP_define && curr.token_enum()!=PP_define_body
81-
&& curr.token_enum()!=PP_elsif && curr.token_enum()!=PP_else && curr.token_enum()!=PP_endif) current_sequence_.pop_back();
84+
if (curr.token_enum() != PP_Identifier && curr.token_enum() != PP_ifndef &&
85+
curr.token_enum() != PP_ifdef && curr.token_enum() != PP_define &&
86+
curr.token_enum() != PP_define_body && curr.token_enum() != PP_elsif &&
87+
curr.token_enum() != PP_else && curr.token_enum() != PP_endif)
88+
current_sequence_.pop_back();
8289
return absl::OkStatus();
8390
}
8491

85-
} // namespace verilog
86-
92+
} // namespace verilog

‎verilog/analysis/flow_tree.h‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
#ifndef VERIBLE_VERILOG_FLOW_TREE_H_
1616
#define VERIBLE_VERILOG_FLOW_TREE_H_
1717

18-
19-
#include <vector>
2018
#include <map>
2119
#include <string>
20+
#include <vector>
21+
2222
#include "absl/status/status.h"
2323
#include "common/lexer/token_stream_adapter.h"
2424
#include "verilog/parser/verilog_token_enum.h"
@@ -27,19 +27,21 @@ namespace verilog {
2727

2828
class FlowTree {
2929
public:
30-
explicit FlowTree(verible::TokenSequence source_sequence): source_sequence_(std::move(source_sequence)){};
30+
explicit FlowTree(verible::TokenSequence source_sequence)
31+
: source_sequence_(std::move(source_sequence)){};
3132

3233
absl::Status GenerateControlFlowTree();
3334
absl::Status DepthFirstSearch(int index);
3435
std::vector<verible::TokenSequence> variants_;
36+
3537
private:
3638
std::vector<int> ifs_;
37-
std::map<int,std::vector<int>> elses_;
38-
std::map<int,std::vector<int>> edges_;
39+
std::map<int, std::vector<int>> elses_;
40+
std::map<int, std::vector<int>> edges_;
3941
verible::TokenSequence source_sequence_;
4042
verible::TokenSequence current_sequence_;
4143
};
4244

43-
} // namespace verilog
45+
} // namespace verilog
4446

45-
#endif // VERIBLE_VERILOG_FLOW_TREE_H_
47+
#endif // VERIBLE_VERILOG_FLOW_TREE_H_

‎verilog/tools/preprocessor/verilog_preprocessor.cc‎

Lines changed: 46 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -20,16 +20,16 @@
2020
#include "absl/status/status.h"
2121
#include "absl/strings/str_cat.h"
2222
#include "absl/strings/string_view.h"
23+
#include "common/lexer/token_stream_adapter.h"
2324
#include "common/util/file_util.h"
2425
#include "common/util/init_command_line.h"
2526
#include "common/util/subcommand.h"
26-
#include "verilog/transform/strip_comments.h"
27-
#include "verilog/parser/verilog_lexer.h"
28-
#include "verilog/preprocessor/verilog_preprocess.h"
29-
#include "common/lexer/token_stream_adapter.h"
27+
#include "verilog/analysis/flow_tree.h"
3028
#include "verilog/analysis/verilog_analyzer.h"
29+
#include "verilog/parser/verilog_lexer.h"
3130
#include "verilog/parser/verilog_token_enum.h"
32-
#include "verilog/analysis/flow_tree.h"
31+
#include "verilog/preprocessor/verilog_preprocess.h"
32+
#include "verilog/transform/strip_comments.h"
3333

3434
using verible::SubcommandArgsRange;
3535
using verible::SubcommandEntry;
@@ -55,67 +55,68 @@ static absl::Status StripComments(const SubcommandArgsRange& args,
5555
return absl::OkStatus();
5656
}
5757

58-
59-
static absl::Status MultipleCU(const SubcommandArgsRange& args,
60-
std::istream&, std::ostream& outs,
61-
std::ostream&) {
58+
static absl::Status MultipleCU(const SubcommandArgsRange& args, std::istream&,
59+
std::ostream& outs, std::ostream&) {
6260
if (args.empty()) {
63-
return absl::InvalidArgumentError(
64-
"Missing file argument.");
61+
return absl::InvalidArgumentError("Missing file argument.");
6562
}
6663

67-
for(auto source_file:args){
64+
for (auto source_file : args) {
6865
std::string source_contents;
6966
if (auto status = verible::file::GetContents(source_file, &source_contents);
7067
!status.ok()) {
7168
return status;
7269
}
7370
verilog::VerilogPreprocess::Config config;
74-
config.filter_branches=1;
75-
//config.expand_macros=1;
71+
config.filter_branches = 1;
72+
// config.expand_macros=1;
7673
verilog::VerilogPreprocess preprocessor(config);
7774
verilog::VerilogLexer lexer(source_contents);
7875
verible::TokenSequence lexed_sequence;
79-
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
80-
lexer.DoNextToken()) {
81-
// For now we will store the syntax tree tokens only, ignoring all the white-space characters.
82-
// however that should be stored to output the source code just like it was, but with conditionals filtered.
83-
if(verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken())) lexed_sequence.push_back(lexer.GetLastToken());
76+
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
77+
lexer.DoNextToken()) {
78+
// For now we will store the syntax tree tokens only, ignoring all the
79+
// white-space characters. however that should be stored to output the
80+
// source code just like it was, but with conditionals filtered.
81+
if (verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken()))
82+
lexed_sequence.push_back(lexer.GetLastToken());
8483
}
8584
verible::TokenStreamView lexed_streamview;
8685
// Initializing the lexed token stream view.
8786
InitTokenStreamView(lexed_sequence, &lexed_streamview);
88-
verilog::VerilogPreprocessData preprocessed_data = preprocessor.ScanStream(lexed_streamview);
87+
verilog::VerilogPreprocessData preprocessed_data =
88+
preprocessor.ScanStream(lexed_streamview);
8989
auto& preprocessed_stream = preprocessed_data.preprocessed_token_stream;
90-
for(auto u:preprocessed_stream) outs<<*u<<'\n'; // output the preprocessed tokens.
91-
for(auto& u:preprocessed_data.errors) outs<<u.error_message<<'\n'; // for debugging.
90+
for (auto u : preprocessed_stream)
91+
outs << *u << '\n'; // output the preprocessed tokens.
92+
for (auto& u : preprocessed_data.errors)
93+
outs << u.error_message << '\n'; // for debugging.
9294
// parsing just as a trial
9395
std::string post_preproc;
94-
for(auto u:preprocessed_stream) post_preproc+=std::string{u->text()};
96+
for (auto u : preprocessed_stream) post_preproc += std::string{u->text()};
9597
std::string source_view{post_preproc};
96-
verilog::VerilogAnalyzer analyzer(source_view,"file1",config);
98+
verilog::VerilogAnalyzer analyzer(source_view, "file1", config);
9799
auto analyze_status = analyzer.Analyze();
98100
const auto& mydata = analyzer.Data().Contents();
99101
/* outs<<mydata; */
100102

101-
102103
/* TODO(karimtera): regarding conditionals
103-
1) Modify VerilogPreprocess config to have a configuration to generate SV source codes for all possible variants.
104-
2) Then use parser, directly from VerilogAnalyzer or from VerilogParser to have less dependences.
105-
3) Now, we should have multiple trees, we need to merge them as described by Tom in Verible's issue.
106-
4) Finally, travese the tree and output the chosen path based on definitions.
104+
1) Modify VerilogPreprocess config to have a configuration to generate SV
105+
source codes for all possible variants. 2) Then use parser, directly from
106+
VerilogAnalyzer or from VerilogParser to have less dependences. 3) Now, we
107+
should have multiple trees, we need to merge them as described by Tom in
108+
Verible's issue. 4) Finally, travese the tree and output the chosen path
109+
based on definitions.
107110
*/
108111
}
109112
return absl::OkStatus();
110113
}
111114

112-
113115
static absl::Status GenerateVariants(const SubcommandArgsRange& args,
114-
std::istream&, std::ostream& outs,
115-
std::ostream&) {
116+
std::istream&, std::ostream& outs,
117+
std::ostream&) {
116118
if (args.empty()) {
117-
return absl::InvalidArgumentError(
118-
"Missing file argument.");
119+
return absl::InvalidArgumentError("Missing file argument.");
119120
}
120121

121122
const char* source_file = args[0];
@@ -126,23 +127,23 @@ static absl::Status GenerateVariants(const SubcommandArgsRange& args,
126127
}
127128
verilog::VerilogLexer lexer(source_contents);
128129
verible::TokenSequence lexed_sequence;
129-
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
130-
lexer.DoNextToken()) {
131-
// For now we will store the syntax tree tokens only, ignoring all the white-space characters.
132-
// however that should be stored to output the source code just like it was.
133-
if(verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken())) lexed_sequence.push_back(lexer.GetLastToken());
130+
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
131+
lexer.DoNextToken()) {
132+
// For now we will store the syntax tree tokens only, ignoring all the
133+
// white-space characters. however that should be stored to output the
134+
// source code just like it was.
135+
if (verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken()))
136+
lexed_sequence.push_back(lexer.GetLastToken());
134137
}
135138

136139
verilog::FlowTree control_flow_tree(lexed_sequence);
137140
auto status = control_flow_tree.GenerateControlFlowTree();
138141
status = control_flow_tree.DepthFirstSearch(0);
139-
int cnt=1;
140-
for(const auto& u:control_flow_tree.variants_){
141-
outs<<"Variant number "<<cnt++<<":\n";
142-
for(auto k:u) outs<<k<<'\n';
142+
int cnt = 1;
143+
for (const auto& u : control_flow_tree.variants_) {
144+
outs << "Variant number " << cnt++ << ":\n";
145+
for (auto k : u) outs << k << '\n';
143146
puts("");
144-
145-
146147
}
147148

148149
return absl::OkStatus();

0 commit comments

Comments
 (0)