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How to configure the formatter in the vscode extension?
formatter
Verilog code formatter issues
#2306
opened Dec 22, 2024 by
gobbedy
Allow verible.filelist per GitHub submodule
language-server
Language server related issues
#2290
opened Nov 11, 2024 by
thomas-woehrle
Formatter is confused by macros
formatter
Verilog code formatter issues
#2289
opened Nov 7, 2024 by
isaacde
how to change lint rule "legacy-generate-region"?
enhancement
New feature or request
good first issue
Good for newcomers
style-linter
Verilog style-linter issues
#2288
opened Nov 7, 2024 by
ddppt-yy
Formatter splits label from assertion on new line unnecessarily
formatter
Verilog code formatter issues
#2284
opened Oct 18, 2024 by
hankhsu1996
Confusion on camelCase versus PascalCase
enhancement
New feature or request
style-linter
Verilog style-linter issues
#2283
opened Oct 12, 2024 by
ukanuk
Improve lint rule help
enhancement
New feature or request
good first issue
Good for newcomers
style-linter
Verilog style-linter issues
#2278
opened Oct 6, 2024 by
IEncinas10
how to use AUTO-expansion in vscode ?
formatter
Verilog code formatter issues
#2258
opened Sep 25, 2024 by
cheungxi
invalid-system-task-function not checked if multiple ifdefs are present in file
style-linter
Verilog style-linter issues
#2256
opened Sep 24, 2024 by
matlupi
Getting Error Unsupported: timing control statement in this location, for wait and @(posedge) statements
language-server
Language server related issues
#2253
opened Sep 19, 2024 by
v4ibhav
localparam type (...)
recognized as wrong syntax
rejects-valid syntax
#2249
opened Sep 15, 2024 by
goekce
Include formatter in VS Code Extension
language-server
Language server related issues
#2245
opened Aug 28, 2024 by
puppuccino
parser refuses bit-selection of concatenation
rejects-valid syntax
If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2244
opened Aug 27, 2024 by
matlupi
Misalignment with comments that end with backslash "\"
formatter
Verilog code formatter issues
#2243
opened Aug 27, 2024 by
Stavegu
Array assignment to wires - parse error on If the parser wrongly rejects syntactically valid code (according to SV-2017).
=
rejects-valid syntax
#2240
opened Aug 21, 2024 by
hzeller
adding a setting for comment alignment
enhancement
New feature or request
style-linter
Verilog style-linter issues
#2239
opened Aug 21, 2024 by
12113004
It is not possible to format the code shown below
formatter
Verilog code formatter issues
#2238
opened Aug 19, 2024 by
17Reset
Is it possible to leave all lines whose beginning wasn't moved as they are? (i.e. to prevent any internal indentation within the line)
formatter
Verilog code formatter issues
#2237
opened Aug 18, 2024 by
avidan-efody
Verible's parser accepts incorrect program/module creation
rejects-valid syntax
If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2233
opened Aug 9, 2024 by
luizademelo
using tick define for delay doesn't work
rejects-valid syntax
If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2232
opened Aug 7, 2024 by
vanjoe
Detect data type and rvalue width mismatches
enhancement
New feature or request
style-linter
Verilog style-linter issues
#2231
opened Aug 5, 2024 by
benjamin051000
How to obtain all symbol tables through textDocumentSymbol request
rejects-valid syntax
If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2228
opened Aug 5, 2024 by
wxllllll
Why is
$random
considered a "forbidden system function or task"?
#2221
opened Aug 2, 2024 by
benjamin051000
support for different type rule into kPortDeclaration
enhancement
New feature or request
style-linter
Verilog style-linter issues
#2220
opened Aug 2, 2024 by
Brughy
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