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@Clo91eaf Clo91eaf commented Dec 8, 2025

Implement from #9026 to fix the implicit clock in ltl.delay

Description:

  • Change ltl.delay signature to: ltl.delay %clock, <edge>, %input, <delay>[, <length>].
  • Update TableGen patterns, canonicalization, lowering, tests, and docs to the new operand order.
  • Folding/merge rules now require same clock+edge to combine delays.

Migration notes:

  • Call sites that create ltl.delay must supply an i1 clock Value and a ClockEdgeAttr (e.g., posedge). Lowering may synthesize a clock (e.g., hw.constant) when none is available.
  • Tests that assumed strict adjacency around ltl.delay may need to either:
    • accept an inserted clock op (use CHECK instead of CHECK-NEXT), or
    • explicitly assert the inserted clock op and keep CHECK-NEXT for ltl.delay.

Testing:

  • Regenerated TableGen rewriters and rebuilt.
  • Updated MLIR tests and FileCheck expectations to be robust against inserted clock constants.

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Clo91eaf commented Dec 8, 2025

@fabianschuiki very very sorry for delay!!! please take a look 🥲

@Clo91eaf Clo91eaf force-pushed the sva_clock branch 5 times, most recently from 6608044 to 98d2a63 Compare December 9, 2025 03:07
@Clo91eaf Clo91eaf closed this by deleting the head repository Dec 9, 2025
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Clo91eaf commented Dec 9, 2025

sorry, i missing delete my repo for some git issue ... 😿
i will create a new pr soon ...

i was trapped for the ci report and try hard to reproduce the errors in my machine, i'm sorry

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