[FIRRTL] Add alternative constraint-based InferWidths pass

include/circt/Dialect/FIRRTL/Passes.td

@@ -358,6 +358,14 @@ def InferWidths : Pass<"firrtl-infer-widths", "firrtl::CircuitOp"> {
   }];
 }
 
+def InferWidths_new : Pass<"firrtl-infer-widths-new", "firrtl::CircuitOp"> {
+  let summary = "Infer the width of types(new)";
+  let description = [{
+    This pass infers the widths of all types throughout a FIRRTL module, and
+    emits diagnostics for types that could not be inferred.(new)
+  }];
+}
+
 def InferResets : Pass<"firrtl-infer-resets", "firrtl::CircuitOp"> {
   let summary = "Infer reset synchronicity and add implicit resets";
   let description = [{

include/circt/Dialect/LLHD/IR/LLHDValueOps.td

@@ -44,3 +44,17 @@ def ConstantTimeOp : LLHDOp<"constant_time",
 
   let hasFolder = 1;
 }
+
+def CurrentTimeOp : LLHDOp<"current_time", [MemoryEffects<[MemRead]>]> {
+  let summary = "Get the current simulation time";
+  let description = [{
+    Materializes the current simulation time as an SSA value. This is equivalent
+    to the `$time`, `$stime`, and `$realtime` system tasks in SystemVerilog, and
+    the `now` keyword in VHDL.
+
+    This operation has a memory read side effect to avoid motion and CSE across
+    `llhd.wait` operations, and other operations that may suspend execution.
+  }];
+  let results = (outs LLHDTimeType:$result);
+  let assemblyFormat = "attr-dict";
+}

include/circt/Firtool/Firtool.h

@@ -96,6 +96,7 @@ class FirtoolOptions {
   bool shouldDisableLayerSink() const { return disableLayerSink; }
   bool shouldDisableOptimization() const { return disableOptimization; }
   bool shouldLowerMemories() const { return lowerMemories; }
+  bool shouldUseNewInferWidths() const { return useNewInferWidths; }
   bool shouldDedup() const { return !noDedup; }
   bool shouldDedupClasses() const { return dedupClasses; }
   bool shouldEnableDebugInfo() const { return enableDebugInfo; }
@@ -416,6 +417,7 @@ class FirtoolOptions {
   bool disableOptimization;
   bool vbToBV;
   bool noDedup;
+  bool useNewInferWidths;
   bool dedupClasses;
   firrtl::CompanionMode companionMode;
   bool noViews;

lib/Conversion/ImportVerilog/Structure.cpp

@@ -803,11 +803,12 @@ Context::convertModuleHeader(const slang::ast::InstanceBodySymbol *module) {
   auto loc = convertLocation(module->location);
   OpBuilder::InsertionGuard g(builder);
 
-  // We only support modules for now. Extension to interfaces and programs
+  // We only support modules and programs for now. Extension to interfaces
   // should be trivial though, since they are essentially the same thing with
   // only minor differences in semantics.
-  if (module->getDefinition().definitionKind !=
-      slang::ast::DefinitionKind::Module) {
+  auto kind = module->getDefinition().definitionKind;
+  if (kind != slang::ast::DefinitionKind::Module &&
+      kind != slang::ast::DefinitionKind::Program) {
     mlir::emitError(loc) << "unsupported definition: "
                          << module->getDefinition().getKindString();
     return {};

lib/Conversion/MooreToCore/MooreToCore.cpp

@@ -2100,6 +2100,17 @@ static LogicalResult convert(FinishMessageBIOp op,
   return success();
 }
 
+//===----------------------------------------------------------------------===//
+// Timing Control Conversion
+//===----------------------------------------------------------------------===//
+
+// moore.builtin.time
+static LogicalResult convert(TimeBIOp op, TimeBIOp::Adaptor adaptor,
+                             ConversionPatternRewriter &rewriter) {
+  rewriter.replaceOpWithNewOp<llhd::CurrentTimeOp>(op);
+  return success();
+}
+
 //===----------------------------------------------------------------------===//
 // Conversion Infrastructure
 //===----------------------------------------------------------------------===//
@@ -2443,6 +2454,9 @@ static void populateOpConversion(ConversionPatternSet &patterns,
   patterns.add<FinishBIOp>(convert);
   patterns.add<FinishMessageBIOp>(convert);
 
+  // Timing control
+  patterns.add<TimeBIOp>(convert);
+
   mlir::populateAnyFunctionOpInterfaceTypeConversionPattern(patterns,
                                                             typeConverter);
   hw::populateHWModuleLikeTypeConversionPattern(

lib/Dialect/FIRRTL/FIRRTLReductions.cpp

@@ -2138,7 +2138,9 @@ void firrtl::FIRRTLReducePatternDialectInterface::populateReducePatterns(
       true);
   patterns.add<PassReduction, 28>(getContext(),
                                   firrtl::createLowerCHIRRTLPass(), true, true);
-  patterns.add<PassReduction, 27>(getContext(), firrtl::createInferWidths(),
+  // patterns.add<PassReduction, 27>(getContext(), firrtl::createInferWidths(),
+  //                                 true, true);
+  patterns.add<PassReduction, 27>(getContext(), firrtl::createInferWidths_new(),
                                   true, true);
   patterns.add<PassReduction, 26>(getContext(), firrtl::createInferResets(),
                                   true, true);

lib/Dialect/FIRRTL/Transforms/CMakeLists.txt

@@ -21,6 +21,7 @@ add_circt_dialect_library(CIRCTFIRRTLTransforms
   InferReadWrite.cpp
   InferResets.cpp
   InferWidths.cpp
+  InferWidths_new.cpp
   InjectDUTHierarchy.cpp
   InnerSymbolDCE.cpp
   LegacyWiring.cpp

lib/Dialect/FIRRTL/Transforms/InferWidths.cpp

@@ -1595,8 +1595,8 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
       })
 
       // Handle the no-ops that don't interact with width inference.
-      .Case<PrintFOp, FFlushOp, SkipOp, StopOp, WhenOp, AssertOp, AssumeOp,
-            UnclockedAssumeIntrinsicOp, CoverOp>([&](auto) {})
+      .Case<AssertOp, AssumeOp, CoverOp, DomainDefineOp, FFlushOp, PrintFOp,
+            SkipOp, StopOp, UnclockedAssumeIntrinsicOp, WhenOp>([&](auto) {})
 
       // Handle instances of other modules.
       .Case<InstanceOp>([&](auto op) {