[FIRRTL] Add UnusedBits test for signed integer

test/Dialect/FIRRTL/simplify-mems.mlir

@@ -336,6 +336,54 @@ firrtl.circuit "UnusedBitsAtEnd" {
 
 // -----
 
+firrtl.circuit "UnusedBitsOfSignedInteger" {
+  firrtl.module public @UnusedBitsOfSignedInteger(
+      in %clock: !firrtl.clock,
+      in %addr: !firrtl.uint<4>,
+      in %in_data: !firrtl.sint<42>,
+      out %result_read: !firrtl.uint<5>) {
+
+    %c1_ui1 = firrtl.constant 1 : !firrtl.uint<1>
+
+    // CHECK: %Memory_read, %Memory_write = firrtl.mem Undefined
+    // CHECK-SAME: !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: sint<5>>
+    // CHECK-SAME: !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: sint<5>, mask: uint<1>>
+    %Memory_read, %Memory_write = firrtl.mem Undefined
+      {
+        depth = 12 : i64,
+        name = "Memory",
+        portNames = ["read", "write"],
+        readLatency = 0 : i32,
+        writeLatency = 1 : i32
+      } :
+        !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: sint<42>>,
+        !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: sint<42>, mask: uint<1>>
+
+    %read_addr = firrtl.subfield %Memory_read[addr] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: sint<42>>
+    firrtl.connect %read_addr, %addr : !firrtl.uint<4>, !firrtl.uint<4>
+    %read_en = firrtl.subfield %Memory_read[en] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: sint<42>>
+    firrtl.connect %read_en, %c1_ui1 : !firrtl.uint<1>, !firrtl.uint<1>
+    %read_clk = firrtl.subfield %Memory_read[clk] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: sint<42>>
+    firrtl.connect %read_clk, %clock : !firrtl.clock, !firrtl.clock
+    %read_data = firrtl.subfield %Memory_read[data] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: sint<42>>
+    %read_data_slice = firrtl.bits %read_data 7 to 3 : (!firrtl.sint<42>) -> !firrtl.uint<5>
+    firrtl.connect %result_read, %read_data_slice : !firrtl.uint<5>, !firrtl.uint<5>
+
+    %write_addr = firrtl.subfield %Memory_write[addr] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: sint<42>, mask: uint<1>>
+    firrtl.connect %write_addr, %addr : !firrtl.uint<4>, !firrtl.uint<4>
+    %write_en = firrtl.subfield %Memory_write[en] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: sint<42>, mask: uint<1>>
+    firrtl.connect %write_en, %c1_ui1 : !firrtl.uint<1>, !firrtl.uint<1>
+    %write_clk = firrtl.subfield %Memory_write[clk] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: sint<42>, mask: uint<1>>
+    firrtl.connect %write_clk, %clock : !firrtl.clock, !firrtl.clock
+    %write_data = firrtl.subfield %Memory_write[data] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: sint<42>, mask: uint<1>>
+    firrtl.connect %write_data, %in_data : !firrtl.sint<42>, !firrtl.sint<42>
+    %write_mask = firrtl.subfield %Memory_write[mask] : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data: sint<42>, mask: uint<1>>
+    firrtl.connect %write_mask, %c1_ui1 : !firrtl.uint<1>, !firrtl.uint<1>
+  }
+}
+
+// -----
+
 firrtl.circuit "OneAddressMasked" {
   firrtl.module public @OneAddressMasked(
       in %clock: !firrtl.clock,