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emit std_compareFN
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@jiahanxie353
jiahanxie353 committed Nov 22, 2024
1 parent 5ef5d11 commit 0db4e8e
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Showing 2 changed files with 77 additions and 2 deletions.
11 changes: 9 additions & 2 deletions lib/Dialect/Calyx/Export/CalyxEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/FormatVariadic.h"
#include "llvm/Support/raw_ostream.h"
#include <bitset>
#include <string>

Expand Down Expand Up @@ -157,6 +158,10 @@ struct ImportTracker {
static constexpr std::string_view sFloatingPoint = "float/mulFN";
return {sFloatingPoint};
})
.Case<CompareFOpIEEE754>([&](auto op) -> FailureOr<StringRef> {
static constexpr std::string_view sFloatingPoint = "float/compareFN";
return {sFloatingPoint};
})
.Default([&](auto op) {
auto diag = op->emitOpError() << "not supported for emission";
return diag;
Expand Down Expand Up @@ -679,7 +684,7 @@ void Emitter::emitComponent(ComponentInterface op) {
emitLibraryPrimTypedByFirstOutputPort(
op, /*calyxLibName=*/{"std_sdiv_pipe"});
})
.Case<AddFOpIEEE754, MulFOpIEEE754>(
.Case<AddFOpIEEE754, MulFOpIEEE754, CompareFOpIEEE754>(
[&](auto op) { emitLibraryFloatingPoint(op); })
.Default([&](auto op) {
emitOpError(op, "not supported for emission inside component");
Expand Down Expand Up @@ -996,8 +1001,10 @@ void Emitter::emitLibraryPrimTypedByFirstOutputPort(

void Emitter::emitLibraryFloatingPoint(Operation *op) {
auto cell = cast<CellInterface>(op);
// magic number for the index of `left/right` input port
size_t inputPortIndex = cell.getInputPorts().size() - 3;
unsigned bitWidth =
cell.getOutputPorts()[0].getType().getIntOrFloatBitWidth();
cell.getInputPorts()[inputPortIndex].getType().getIntOrFloatBitWidth();
// Since Calyx interacts with HardFloat, we'll also only be using expWidth and
// sigWidth. See
// http://www.jhauser.us/arithmetic/HardFloat-1/doc/HardFloat-Verilog.html
Expand Down
68 changes: 68 additions & 0 deletions test/Dialect/Calyx/emit.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -384,3 +384,71 @@ module attributes {calyx.entrypoint = "main"} {
} {toplevel}
}

// -----

module attributes {calyx.entrypoint = "main"} {
// CHECK: import "primitives/float/compareFN.futil";
calyx.component @main(%in0: i32, %clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%out0: i1, %done: i1 {done}) {
%cst = calyx.constant @cst_0 <4.200000e+00 : f32> : i32
%true = hw.constant true
%std_and_1.left, %std_and_1.right, %std_and_1.out = calyx.std_and @std_and_1 : i1, i1, i1
%std_and_0.left, %std_and_0.right, %std_and_0.out = calyx.std_and @std_and_0 : i1, i1, i1
%unordered_port_0_reg.in, %unordered_port_0_reg.write_en, %unordered_port_0_reg.clk, %unordered_port_0_reg.reset, %unordered_port_0_reg.out, %unordered_port_0_reg.done = calyx.register @unordered_port_0_reg : i1, i1, i1, i1, i1, i1
%compare_port_0_reg.in, %compare_port_0_reg.write_en, %compare_port_0_reg.clk, %compare_port_0_reg.reset, %compare_port_0_reg.out, %compare_port_0_reg.done = calyx.register @compare_port_0_reg : i1, i1, i1, i1, i1, i1
%cmpf_0_reg.in, %cmpf_0_reg.write_en, %cmpf_0_reg.clk, %cmpf_0_reg.reset, %cmpf_0_reg.out, %cmpf_0_reg.done = calyx.register @cmpf_0_reg : i1, i1, i1, i1, i1, i1
// CHECK-DAG: std_compareFN_0 = std_compareFN(8, 24, 32);
%std_compareFN_0.clk, %std_compareFN_0.reset, %std_compareFN_0.go, %std_compareFN_0.left, %std_compareFN_0.right, %std_compareFN_0.signaling, %std_compareFN_0.lt, %std_compareFN_0.eq, %std_compareFN_0.gt, %std_compareFN_0.unordered, %std_compareFN_0.exceptionalFlags, %std_compareFN_0.done = calyx.ieee754.compare @std_compareFN_0 : i1, i1, i1, i32, i32, i1, i1, i1, i1, i1, i5, i1
%ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i1, i1, i1, i1, i1, i1
calyx.wires {
calyx.assign %out0 = %ret_arg0_reg.out : i1
// CHECK-LABEL: group bb0_0 {
// CHECK-NEXT: std_compareFN_0.left = in0;
// CHECK-NEXT: std_compareFN_0.right = cst_0.out;
// CHECK-NEXT: compare_port_0_reg.write_en = std_compareFN_0.done;
// CHECK-NEXT: compare_port_0_reg.in = std_compareFN_0.eq;
// CHECK-NEXT: unordered_port_0_reg.write_en = std_compareFN_0.done;
// CHECK-NEXT: unordered_port_0_reg.in = !std_compareFN_0.unordered ? 1'd1;
// CHECK-NEXT: std_and_0.left = compare_port_0_reg.out;
// CHECK-NEXT: std_and_0.right = unordered_port_0_reg.out;
// CHECK-NEXT: std_and_1.left = compare_port_0_reg.done;
// CHECK-NEXT: std_and_1.right = unordered_port_0_reg.done;
// CHECK-NEXT: cmpf_0_reg.in = std_and_0.out;
// CHECK-NEXT: cmpf_0_reg.write_en = std_and_1.out;
// CHECK-NEXT: std_compareFN_0.go = !std_compareFN_0.done ? 1'd1;
// CHECK-NEXT: bb0_0[done] = cmpf_0_reg.done;
// CHECK-NEXT: }
calyx.group @bb0_0 {
calyx.assign %std_compareFN_0.left = %in0 : i32
calyx.assign %std_compareFN_0.right = %cst : i32
calyx.assign %compare_port_0_reg.write_en = %std_compareFN_0.done : i1
calyx.assign %compare_port_0_reg.in = %std_compareFN_0.eq : i1
calyx.assign %unordered_port_0_reg.write_en = %std_compareFN_0.done : i1
%0 = comb.xor %std_compareFN_0.unordered, %true : i1
calyx.assign %unordered_port_0_reg.in = %0 ? %true : i1
calyx.assign %std_and_0.left = %compare_port_0_reg.out : i1
calyx.assign %std_and_0.right = %unordered_port_0_reg.out : i1
calyx.assign %std_and_1.left = %compare_port_0_reg.done : i1
calyx.assign %std_and_1.right = %unordered_port_0_reg.done : i1
calyx.assign %cmpf_0_reg.in = %std_and_0.out : i1
calyx.assign %cmpf_0_reg.write_en = %std_and_1.out : i1
%1 = comb.xor %std_compareFN_0.done, %true : i1
calyx.assign %std_compareFN_0.go = %1 ? %true : i1
calyx.group_done %cmpf_0_reg.done : i1
}
calyx.group @ret_assign_0 {
calyx.assign %ret_arg0_reg.in = %cmpf_0_reg.out : i1
calyx.assign %ret_arg0_reg.write_en = %true : i1
calyx.group_done %ret_arg0_reg.done : i1
}
}
calyx.control {
calyx.seq {
calyx.seq {
calyx.enable @bb0_0
calyx.enable @ret_assign_0
}
}
}
} {toplevel}
}

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