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2021 11 22 sync
Alexey Bader edited this page Nov 22, 2021
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https://reviews.llvm.org/D71016 - [SYCL] Implement OpenCL kernel function generation. TODO items:
- Integrate https://github.com/intel/llvm/pull/3892 into https://reviews.llvm.org/D71016
- Move functionality from SemaSYCL to CodeGen library
Participants: Alexey Bader (Intel), Mariya Podchischaeva (Intel), Elizabeth Andrews (Intel), Premanand M Rao (Intel), Victor Lomuller (Codeplay), Gauthier Harnisch (Xilinx), Ronan Keryell (Xilinx) Luc Forget (Xilinx)
- Victor: the way it's implemented in the patch is the right one. SPIR-V doesn't support this feature.
- AlexeyB: can zero length arrays be supported by non-SPIR targets?
- Victor: Potentially yes, so we can lift this restriction later if needed.
- Ronan: it's not clear how we ensure consistent data layout for such arrays between the host and devices, so it's better to restrict usage for now.
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Zahira: I've addressed one of two major comments -
sycl_special_classattribute has been added to detect SYCL classes for special handling by the compiler. -
Maryia: Does it make sense to commit
sycl_special_classattribute separately? 71016 is quite big already, so moving to a separate review request should simplify the work for reviewers. - Zahira: I can do this, but we need SemaSYCL changes to validate "code generation" logic for this attribute.
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Maryia: Right. We can add simple tests with the attribute and extend testing with SemaSYCL changes. Here is a good example of how we applied similar approach with
sycl_kernelattribute. https://reviews.llvm.org/D60455
- AlexeyB: Last week D112404 [SPIR-V] Add translator tool (llvm.org) has been merged to llorg. We have similar change for SYCL, so we can consider this work as being upstreamed once we merge it with DPC++ compiler changes.