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2019 07 22 meeting notes

Alexey Bader edited this page Aug 5, 2019 · 7 revisions

Agenda

Meeting notes

Participants: Alexey Bader(Intel), Mike Kinsner(Intel), James Brodman(Intel), Ronan Keryell(Xilinx), Andrew Gozillon(Xilinx), Victor Lomuller(Codeplay), ... (I think I didn't capture a couple of people)

Opens

No

Create a continuous integration framework (https://github.com/triSYCL/sycl/issues/53)

Ronan: There is no continuous integration system for Xilinx FPGA. We would like to configure something like travis to catch Xilinx FPGA specific issues introduced by changes in https://github.com/intel/llvm project.

Alexey: Intel team uses internal machines for CI system for several reasons. Open CI systems like travis have a number of limitations (e.g. job execution time < 1h, no more than N parallel jobs, etc.) and in addition to that this project requires specific HW (e.g. access to GPUs).

Alexey: to test Intel FPGA HW we use "FPGA emulator" running SYCL code on CPU, which is much faster than testing on real HW.

LLVM dev meeting (22 - 23 October)

Ronan: Is there any interest in organizing SYCL specific session at LLVM developers meeting? Round table or BOF.

Victor: BOF about SYCL or more about offloading?

James: Generality could be good, but we need to avoid making it CUDA topic.

Alexey: Who should send a proposal?

Ronan: Intel should push as it drives the upstreaming effort. BOF/panel participants include multiple companies: Intel, Xilinx, Codeplay, ANL, RedHat?.

LIT tests failures on Xilinx

Andrew: A lot of tests failing. Need to resolve generic pointers.

Alexey: Please, open an issue and ask Andrew Savonichev for advice how to handle these failures.

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