Passing external defines and incdirs to the preprocessor.

[karimtera]

"VerilogPreprocess":

• Adds "PreprocessingInfo" to storing external defines and incdirs.
• Adds a public function "SetPreprocessingInfo()" to set these info.

The preprocessor tool:

• Modifies "PreprocessSingleFile()" arguments to accept a "PreprocessingInfo", rather than just defines.

Implementation details:

• Needed to move FileList to a separate file outside verilog_project.h to avoid dependency cycle.

[karimtera]

I don't understand why there was a conflict on preprocessor/BUILD.

[hzeller]

I think we should move the actual implementation of the include feature to its own pull request (see comment, I think we should see if we can re-use some functionality).

So in this change, just breaking out the FileList into its own file and the corresponding changes. Then we can concentrate on the actual include implementation.

[hzeller]

Did you have a look how the kythe extractor and/or project_tool (I forgot where ti is implemented) does the include handling ?
Ideally we keep the ownership of the full file in one place (and then the string ownership where the tokens are pointing to is clear).

[karimtera]

No, I will try to find it.

[hzeller]

w.r.t the BUILD conflict, I was running buildifier, so that moved some lines around.

essentially

buildifier $(find . -name BUILD)

This was the change 5910541

[codecov-commenter]

Codecov Report

Merging #1440 (9407e13) into master (d7d3259) will increase coverage by 0.00%.
The diff coverage is 100.00%.

@@           Coverage Diff           @@
##           master    #1440   +/-   ##
=======================================
  Coverage   92.94%   92.94%           
=======================================
  Files         342      343    +1     
  Lines       24158    24159    +1     
=======================================
+ Hits        22453    22454    +1     
  Misses       1705     1705           

Impacted Files	Coverage Δ
verilog/analysis/verilog_project.h	100.00% <ø> (ø)
verilog/preprocessor/verilog_preprocess.h	100.00% <ø> (ø)
verilog/analysis/verilog_filelist.h	100.00% <100.00%> (ø)
verilog/analysis/verilog_project.cc	94.44% <100.00%> (ø)
verilog/preprocessor/verilog_preprocess.cc	92.74% <100.00%> (+0.04%)	⬆️
verilog/tools/kythe/verilog_kythe_extractor.cc	77.02% <100.00%> (ø)
verilog/tools/preprocessor/verilog_preprocessor.cc	89.83% <100.00%> (-0.09%)	⬇️
verilog/tools/project/project_tool.cc	93.20% <100.00%> (ø)

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[hzeller]

LGTM! Thanks, merged.