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Add PPR support #5

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Add PPR support #5

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@gmarull gmarull commented Feb 1, 2024 •
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Testing:

# app, with PPR boot + ppr
rm -rf build_*
west build -b nrf54h20pdk_nrf54h20_cpuapp samples/hello_world -d build_app -S nordic-ppr
west build -b nrf54h20pdk_nrf54h20_cpuppr samples/hello_world -d build_ppr
west flash -d build_ppr && west flash -d build_app

anangl and others added 20 commits January 31, 2024 18:22
@anangl
dts: Add and extend Nordic bindings needed for nRF54H20
83022ff 
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).

Signed-off-by: Grzegorz Swiderski <[email protected]>
Signed-off-by: Gerard Marull-Paretas <[email protected]>
Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
dts: Add initial support for nRF54H20 EngA SoC
afdb528 
Add definition of the nRF54H20 SoC revision EngA with its Application,
Radio, and Peripheral Processor (PPR) cores and basic peripherals:
GRTC, GPIOs, GPIOTE, and UARTs.

Signed-off-by: Grzegorz Swiderski <[email protected]>
Signed-off-by: Gerard Marull-Paretas <[email protected]>
Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
modules: hal_nordic: nrfx_glue: Include cmsis_core_m_defaults.h
b80b938 
... to cover missing __ICACHE_PRESENT and __DCACHE_PRESENT symbols that
should be defined in MDK files.

Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
modules: hal_nordic: Use common nrfx_config section for GRTC
6218e89 
Move code that prepares `NRFX_CONFIG_GRTC_*` definitions based on
information from devicetree from the nRF54L15 nrfx_config header
to the global one, so that the code can be used by nRF54H20, too.

The checks that validate owned-channels and child-owned-channels
DT properties are moved to the nrf_grtc_timer driver so that
the global nrfx_config is not polluted unnecessarily.

The default values in nrfx_config_nrf54l15_enga_application.h
are restored to those from the corresponding template file.

Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
soc: nordic: Add initial support for nRF54H20 EngA
f6c5f27 
Add nrfx and Kconfig related infrastructure plus SoC initialization
code to allow building for nRF54H20 targets (Application and Radio
cores).

Signed-off-by: Gerard Marull-Paretas <[email protected]>
Signed-off-by: Andrzej Głąbek <[email protected]>
@57300 @anangl
modules: hal_nordic: Set SOC_SVD_FILE
7e5dc6d 
This CMake variable contains a path to a CMSIS-SVD file from nRF MDK,
which describes the selected Nordic SoC.

Initially, this will be used as an argument to nrf-regtool.

Signed-off-by: Grzegorz Swiderski <[email protected]>
@57300 @anangl
modules: hal_nordic: Integrate nrf-regtool
76610e0 
nrf-regtool is a Python utility from Nordic Semiconductor, which is used
for generating binary files with register values for given peripherals.
It sources the descriptions of peripheral registers from CMSIS-SVD files
(typically ones bundled with nRF MDK).

For some peripherals, such as UICR, nrf-regtool supports parsing values
from devicetree as well, based on the bindings already found in Zephyr.

Currently, this tool is not submitted as a script to Zephyr, but it can
be installed from PyPI.

Having nrf-regtool installed is recommended when working with nRF54H20.
Booting the Application or Radiocore CPU requires flashing not only its
firmware, but also its respective UICR instance. On this SoC, the UICR
is used to assign ownership of global hardware resources, including
memory and peripherals, to individual cores. The Zephyr build system can
call nrf-regtool to generate the UICR based on devicetree, to reflect
the boot-time hardware configuration required for a given application.
The generated `uicr.hex` is then merged with `zephyr.hex`, so that they
can be flashed together using west.

The build system integration takes the form of a CMake package, which
includes a version check and reusable components; over time, some of
these components can be reused by sysbuild. This package is located in
the `hal_nordic` module, because it depends on the `SOC_SVD_FILE` CMake
variable, which is defined there as well.

Signed-off-by: Grzegorz Swiderski <[email protected]>
@anangl
drivers: serial: Kconfig.nrfx: Filter out options unsupported on nRF5…
1318535 
…4H20

On nRF54H20, only the new shim can be used and the enhanced poll out
cannot be enabled since there is no DPPI support for this SoC yet.

Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
drivers: serial: nrfx: Allow new UARTE instances to be used
4d2f7ec 
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.

Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
drivers: timer: nrf_grtc_timer: Add dependency on nRF clock control
adc7c48 
... in the related parts, so that the driver can be used on nRF54H20
where the clock control is not present yet.

Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
tests: arm_irq_vector_table: Add special handling for nRF54H20
b9f8891 
Different set of IRQ lines need to be used for this SoC and the CLOCK
IRQ is not to be installed in the vector table.

Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
dts: nordic: Include input-event-codes.h from nrf_common.dtsi
7d08b6c 
... so that there is no need to include that header individually
for every added board based on an nRF SoC.

Signed-off-by: Andrzej Głąbek <[email protected]>
@gmarull @anangl
scripts: west: runners: nrfjprog: add option to not erase
bc2bfb0 
On some new SoCs, the erase option is not required, so introduce a new
option that doesn't set any erase mode.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull @anangl
scripts: west: runners: nrfjprog: add erasepage op
79cd69e 
Add a new operation that allows erasing pages.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull @anangl
scripts: west: runners: nrfjprog: add basic support for nRF54H series
21af9c2 
Add basic support to flash application and/or radio core for nRF54H
series. Note that features like merged hexes present in nRF53 series is
not supported. Flashing other cores like PPR/VPR is not supported yet.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@anangl
boards: arm: Add initial support for nRF54H20 PDK
c677513 
Add targets that allows building for the Application and Radio cores
in the nRF54H20 SoC on the nRF54H20 PDK board.

Signed-off-by: Grzegorz Swiderski <[email protected]>
Signed-off-by: Gerard Marull-Paretas <[email protected]>
Signed-off-by: Andrzej Głąbek <[email protected]>
@anangl
tests: lib: cpp: Exclude cpp98 test on nRF54H20
1217c66 
Similar to nRF54L15, the MDK files in HAL for this SoC are not
compatible with C++98, so currently the test cannot be performed
on this SoC.

Signed-off-by: Andrzej Głąbek <[email protected]>
@gmarull
dts: bindings: riscv: nordic,vpr-coprocessor: rename src/dst props
809e8fb 
Use names that are more explicit: execution-memory and source-memory.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
drivers: misc: nordic_vpr_launcher: initial version
d76ac03 
Add a custom driver that takes care of loading and launching RISC-V VPR
cores found on the new nRF54 SoCs.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
boards: nrf54h20pdk_nrf54h20: define cpuppr_vpr source/execution areas
413253c 
So that we only need to enable cpuppr_ram3x_region and cpuppr_vpr to
enable PPR.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull gmarull mentioned this pull request Feb 1, 2024
Closed
@gmarull gmarull force-pushed the ppr-support branch 2 times, most recently from 4cd5030 to 01571d8 Compare February 1, 2024 10:58
@gmarull gmarull force-pushed the ppr-support branch 6 times, most recently from 2ea0036 to 21e3a25 Compare February 1, 2024 13:27
@gmarull
dts: bindings: cpu: s/nordic,riscv/nordic,vpr
b1bf8a2 
The core is named "VPR".

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
dts: bindings: cpu: nordic,vpr: add nordic,bus-width property
2939553 
To specify the CPU bus width.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
dts: common: nordic: nrf54h20_enga: add nordic,bus-width to PPR CPU
85110bb 
It is now a required property.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
modules: hal_nordic: add configuration for nRF54H PPR core
e1879b2 
Add nrfx configuration file and CMake injected definitions to make the
nrfx HAL work for nRF54H PPR core.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull gmarull requested review from 57300 and anangl February 2, 2024 09:04
gmarull
gmarull commented Feb 2, 2024
View reviewed changes
soc/riscv/nordic_nrf/common/vpr/Kconfig
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0

config RISCV_CORE_NORDIC_VPR
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note for future: we should think of moving core-dependent code to arch/riscv/cores, or soc/common since we could potentially have independent socs running the same riscv cores. not likely the case for VPR though.

gmarull
gmarull commented Feb 2, 2024
View reviewed changes
soc/riscv/nordic_nrf/common/vpr/soc_irq.c
Comment on lines +8 to +26
void arch_irq_enable(unsigned int irq)
{
nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, true);
}

void arch_irq_disable(unsigned int irq)
{
nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, false);
}

void arch_irq_priority_set(unsigned int irq, unsigned int prio)
{
nrf_vpr_clic_int_priority_set(NRF_VPRCLIC, irq, prio);
}

int arch_irq_is_enabled(unsigned int irq)
{
return nrf_vpr_clic_int_enable_check(NRF_VPRCLIC, irq);
}
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for future: we should have a generic CLIC driver, but things are still a bit messy in riscv.

@gmarull
scripts: kconfig: functions: add dt_chosen_partition_addr_int|hex
6c0eeae 
dt_chosen_partition_addr_int|hex allow obtaining the absolute address of
a partition, which is the result of the grandparent node address plus
the partition node address.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
soc: common: nordic_nrf: move pinctrl_soc.h to a common dir
43e9c69 
Because both, RISC-V and ARM cores share the same pinctrl driver. The
top level common folder will disappear with the introduction of HWMv2,
where multi-arch SoCs will be well supported.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
soc: arm: nordic_nrf: move Kconfig.peripherals to common folder
8769f3d 
Because RISC-V cores also need to include this file, so it is no longer
ARM specific.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
soc: riscv: nordic_nrf: add initial support for VPR core
029e448 
Add initial support for the VPR RISC-V core found in the new nRF54 SoCs.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
soc: riscv: nordic_nrf: nrf54h: introduce PPR support
5f43588 
Add support for the nRF54H PPR (Peripheral Processor), based on the VPR
RISC-V core.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
boards: riscv: add nrf54h20pdk_nrf54h20_cpuppr
7832539 
Add a board that allows to build for the nRF54H20 PPR RISC-V core.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull gmarull requested a review from 57300 February 2, 2024 09:22
@anangl
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anangl commented Feb 2, 2024

Integrated into zephyrproject-rtos#68043.

@anangl anangl closed this Feb 2, 2024
@gmarull gmarull deleted the ppr-support branch February 2, 2024 12:08
anangl pushed a commit that referenced this pull request Nov 4, 2024
@swkim101 @aescolar
Bluetooth: userchan: fix buffer overflow in hci_packet_complete()
88de271 
hci_packet_complete(buf, buf_size) should check whether buf_size is
enough.
For instance, hci_packet_complete can receive buf with buf_size 1,
leading to the buffer overflow in cmd->param_len, which is buf[3].
This can happen when rx_thread() receives two frames in 512 bytes
and the first frame size is 511. Then, rx_thread() will call
hci_packet_complete() with 1.

==5==ERROR: AddressSanitizer: global-buffer-overflow on address
0x000000ad81c2 at pc 0x0000005279b3 bp 0x7fffe74f5b70 sp 0x7fffe74f5b68

READ of size 2 at 0x000000ad81c2 thread T6
    #0 0x5279b2  (/root/zephyr.exe+0x5279b2)
    #1 0x4d697d  (/root/zephyr.exe+0x4d697d)
    #2 0x7ffff60e5daa  (/lib/x86_64-linux-gnu/libc.so.6+0x89daa)
(BuildId: 2e01923fea4ad9f7fa50fe24e0f3385a45a6cd1c)

0x000000ad81c2 is located 2 bytes to the right of global variable
'rx_thread.frame' defined in 'zephyr/drivers/bluetooth/hci/userchan.c'
(0xad7fc0) of size 512
SUMMARY: AddressSanitizer: global-buffer-overflow
(/root/zephyr.exe+0x5279b2)
Thread T6 created by T2 here:
    #0 0x48c17c  (/root/zephyr.exe+0x48c17c)
    #1 0x530192  (/root/zephyr.exe+0x530192)
    #2 0x4dcc22  (/root/zephyr.exe+0x4dcc22)

Thread T2 created by T1 here:
    #0 0x48c17c  (/root/zephyr.exe+0x48c17c)
    #1 0x530192  (/root/zephyr.exe+0x530192)
    #2 0x4dcc22  (/root/zephyr.exe+0x4dcc22)

Thread T1 created by T0 here:
    #0 0x48c17c  (/root/zephyr.exe+0x48c17c)
    #1 0x52f36c  (/root/zephyr.exe+0x52f36c)
    #2 0x5371dc  (/root/zephyr.exe+0x5371dc)
    #3 0x5312a6  (/root/zephyr.exe+0x5312a6)
    #4 0x52ed7b  (/root/zephyr.exe+0x52ed7b)
    #5 0x52eddd  (/root/zephyr.exe+0x52eddd)
    #6 0x7ffff6083c89  (/lib/x86_64-linux-gnu/libc.so.6+0x27c89)
(BuildId: 2e01923fea4ad9f7fa50fe24e0f3385a45a6cd1c)

==5==ABORTING

Signed-off-by: Sungwoo Kim <[email protected]>
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@57300 57300 57300 approved these changes

@masz-nordic masz-nordic masz-nordic approved these changes

@anangl anangl anangl approved these changes

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@gmarull @anangl @masz-nordic @57300