Add PPR support

boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NRF54H20PDK_NRF54H20_CPUAPP
+	bool "nRF54H20 PDK nRF54H20 Application MCU"
+	depends on SOC_NRF54H20_ENGA_CPUAPP
+
+config BOARD_NRF54H20PDK_NRF54H20_CPURAD
+	bool "nRF54H20 PDK nRF54H20 Radio MCU"
+	depends on SOC_NRF54H20_ENGA_CPURAD

boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NRF54H20PDK_NRF54H20_CPUAPP
+
+config BOARD
+	default "nrf54h20pdk_nrf54h20_cpuapp"
+
+endif # BOARD_NRF54H20PDK_NRF54H20_CPUAPP
+
+if BOARD_NRF54H20PDK_NRF54H20_CPURAD
+
+config BOARD
+	default "nrf54h20pdk_nrf54h20_cpurad"
+
+endif # BOARD_NRF54H20PDK_NRF54H20_CPURAD

boards/arm/nrf54h20pdk_nrf54h20/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)

boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst

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+.. _nrf54h20pdk_nrf54h20:
+
+nRF54H20 PDK
+############
+
+Overview
+********
+
+The nRF54H20 PDK is a single-board preview development kit for evaluation
+and development on the Nordic nRF54H20 System-on-Chip (SoC).
+
+The nRF54H20 is a multicore SoC with:
+
+* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
+  Extensions, running at up to 320 MHz, referred to as the **application core**
+* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
+  Extensions, running at up to 256 MHz, referred to as the **radio core**.
+
+The ``nrf54h20pdk_nrf54h20_cpuapp`` build target provides support for
+the application core on the nRF54H20 SoC.
+The ``nrf54h20pdk_nrf54h20_cpurad`` build target provides support for
+the radio core on the nRF54H20 SoC.
+
+nRF54H20 SoC provides support for the following devices:
+
+* :abbr:`ADC (Analog to Digital Converter)`
+* CLOCK
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`GPIOTE (General Purpose Input Output tasks and events)`
+* :abbr:`GRTC (Global real-time counter)`
+* :abbr:`I2C (Inter-Integrated Circuit)`
+* MRAM
+* :abbr:`PWM (Pulse Width Modulation)`
+* RADIO (Bluetooth Low Energy and 802.15.4)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UART (Universal asynchronous receiver-transmitter)`
+* :abbr:`USB (Universal Serial Bus)`
+* :abbr:`WDT (Watchdog Timer)`
+
+.. figure:: img/nrf54h20pdk_nrf54h20.webp
+     :align: center
+     :alt: nRF54H20 PDK
+
+     nRF54H20 PDK (Credit: Nordic Semiconductor)
+
+Hardware
+********
+
+nRF54H20 PDK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+Supported Features
+==================
+
+The nrf54h20pdk_nrf54h20_cpuapp board configuration supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| GPIOTE    | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| GRTC      | on-chip    | system clock         |
++-----------+------------+----------------------+
+| UART      | on-chip    | serial               |
++-----------+------------+----------------------+
+
+The nrf54h20pdk_nrf54h20_cpurad board configuration supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| GPIOTE    | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| GRTC      | on-chip    | system clock         |
++-----------+------------+----------------------+
+| UARTE     | on-chip    | serial               |
++-----------+------------+----------------------+
+
+Other hardware features have not been enabled yet for this board.
+
+Connections and IOs
+===================
+
+LEDs
+----
+
+* LED1 (green) = P9.0
+* LED2 (green) = P9.1
+* LED3 (green) = P9.2
+* LED4 (green) = P9.3
+
+Push buttons
+------------
+
+* BUTTON1 = P0.8
+* BUTTON2 = P0.9
+* BUTTON3 = P0.10
+* BUTTON4 = P0.11
+* BOOT = SW1 = boot/reset
+
+Programming and Debugging
+*************************
+
+Applications for both the ``nrf54h20pdk_nrf54h20_cpuapp`` and
+``nrf54h20pdk_nrf54h20_cpurad`` targets can be built, flashed,
+and debugged in the usual way. See :ref:`build_an_application`
+and :ref:`application_run` for more details on building and running.
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :ref:`hello_world`
+application.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the nRF54H20 PDK, complete the following steps:
+
+First, connect the nRF54H20 PDK to you computer using the IMCU USB port on the PDK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nrf54h20pdk_nrf54h20_cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons in the nRF54H20 PDK
+************************************************
+
+There are 2 samples that allow you to test that the buttons (switches) and LEDs
+on the board are working properly with Zephyr:
+
+* :zephyr:code-sample:`blinky`
+* :zephyr:code-sample:`button`
+
+You can build and flash the examples to make sure Zephyr is running correctly on
+your board. The button and LED definitions can be found in
+:zephyr_file:`boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts`.

boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi

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+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	reserved-memory {
+		cpuppr_ram3x_region: memory@2fc00000 {
+			compatible = "nordic,owned-memory";
+			reg = <0x2fc00000 DT_SIZE_K(28)>;
+			status = "disabled";
+			perm-read;
+			perm-write;
+			perm-execute;
+		};
+
+		ram3x_dma_region: memory@2fc07000 {
+			compatible = "nordic,owned-memory";
+			reg = <0x2fc07000 DT_SIZE_K(4)>;
+			status = "disabled";
+			perm-read;
+			perm-write;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x2fc07000 0x1000>;
+
+			cpuapp_dma_region: memory@680 {
+				compatible = "zephyr,memory-region";
+				reg = <0x680 DT_SIZE_K(2)>;
+				status = "disabled";
+				#memory-region-cells = <0>;
+				zephyr,memory-region = "DMA_RAM3x_APP";
+			};
+
+			cpurad_dma_region: memory@e80 {
+				compatible = "zephyr,memory-region";
+				reg = <0xe80 0x80>;
+				status = "disabled";
+				#memory-region-cells = <0>;
+				zephyr,memory-region = "DMA_RAM3x_RAD";
+			};
+		};
+	};
+};
+
+&mram1x {
+	cpurad_rx_partitions: cpurad-rx-partitions {
+		compatible = "nordic,owned-partitions", "fixed-partitions";
+		status = "disabled";
+		perm-read;
+		perm-execute;
+		perm-secure;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpurad_slot0_partition: partition@66000 {
+			reg = <0x66000 DT_SIZE_K(256)>;
+		};
+	};
+
+	cpuapp_rx_partitions: cpuapp-rx-partitions {
+		compatible = "nordic,owned-partitions", "fixed-partitions";
+		status = "disabled";
+		perm-read;
+		perm-execute;
+		perm-secure;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuapp_slot0_partition: partition@a6000 {
+			reg = <0xa6000 DT_SIZE_K(512)>;
+		};
+
+		cpuppr_code_partition: partition@126000 {
+			reg = <0x126000 DT_SIZE_K(28)>;
+		};
+	};
+};

boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi

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+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart135_default: uart135_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RTS, 1, 0)>;
+		};
+
+		group2 {
+			bias-pull-up;
+			psels = <NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_CTS, 1, 6)>;
+		};
+	};
+
+	/omit-if-no-ref/ uart135_sleep: uart135_sleep {
+		group1 {
+			low-power-enable;
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_RTS, 1, 0)>,
+				<NRF_PSEL(UART_CTS, 1, 6)>;
+		};
+	};
+
+	/omit-if-no-ref/ uart136_default: uart136_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 4)>,
+				<NRF_PSEL(UART_RTS, 2, 0)>;
+		};
+
+		group2 {
+			bias-pull-up;
+			psels = <NRF_PSEL(UART_RX, 2, 5)>,
+				<NRF_PSEL(UART_CTS, 2, 6)>;
+		};
+	};
+
+	/omit-if-no-ref/ uart136_sleep: uart136_sleep {
+		group1 {
+			low-power-enable;
+			psels = <NRF_PSEL(UART_TX, 2, 4)>,
+				<NRF_PSEL(UART_RX, 2, 5)>,
+				<NRF_PSEL(UART_RTS, 2, 0)>,
+				<NRF_PSEL(UART_CTS, 2, 6)>;
+		};
+	};
+};