Genesys2

example/Genesys2/fpga/Makefile

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+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	djtgcfg prog -d Genesys2 --index 0 --file fpga/fpga.bit

example/Genesys2/fpga/README.md

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+# Verilog Ethernet Genesys2 Example Design
+
+## Introduction
+
+This example design targets the Digilent Genesys FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+FPGA: xc7k325tffg900-2
+PHY: Realtek RTL8211E-VL
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the Nexys Video board with the Digilent command
+line tools.  Then run netcat -u 192.168.1.128 1234 to open a UDP connection to
+port 1234.  Any text entered into netcat will be echoed back after pressing
+enter.  
+
+

example/Genesys2/fpga/common/vivado.mk

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+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: clean fpga
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+tmpclean:
+	-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean: tmpclean
+	-rm -rf *.bit program.tcl
+
+distclean: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+%.xpr: Makefile $(XCI_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
+	echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
+	for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
+	for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
+	echo "exit" >> create_project.tcl
+	vivado -mode batch -source create_project.tcl
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	echo "exit" >> run_synth.tcl
+	vivado -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "exit" >> run_impl.tcl
+	vivado -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	echo "exit" >> generate_bit.tcl
+	vivado -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do let COUNT=COUNT+1; done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

example/Genesys2/fpga/eth.xdc

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+# Ethernet constraints
+
+# IDELAY on RGMII from PHY chip
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+

example/Genesys2/fpga/fpga.xdc

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+# XDC constraints for the Digilent Nexys Video board
+# part: xc7a200tsbg484-1
+
+# General configuration
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+# 200 MHz clock
+set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+#Comment this out if you use clock wizard
+#create_clock -period 5.000 -name clk [get_ports sysclk_p]
+set_clock_groups -asynchronous -group [get_clocks clk -include_generated_clocks]
+
+# LEDs 
+set_property -dict {LOC T28 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
+set_property -dict {LOC V19 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
+set_property -dict {LOC U30 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[2]}]
+set_property -dict {LOC U29 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[3]}]
+set_property -dict {LOC V20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[4]}]
+set_property -dict {LOC V26 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[5]}]
+set_property -dict {LOC W24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[6]}]
+set_property -dict {LOC W23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[7]}]
+
+# Reset button
+set_property -dict {LOC R19 IOSTANDARD LVCMOS33} [get_ports reset_n]
+
+# Push buttons
+set_property -dict {LOC B19 IOSTANDARD LVCMOS12} [get_ports btnu]
+set_property -dict {LOC M20 IOSTANDARD LVCMOS12} [get_ports btnl]
+set_property -dict {LOC M19 IOSTANDARD LVCMOS12} [get_ports btnd]
+set_property -dict {LOC C19 IOSTANDARD LVCMOS12} [get_ports btnr]
+set_property -dict {LOC E18 IOSTANDARD LVCMOS12} [get_ports btnc]
+
+# Toggle switches
+set_property -dict {LOC G19 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
+set_property -dict {LOC G25 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
+set_property -dict {LOC H24 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
+set_property -dict {LOC K19 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
+set_property -dict {LOC N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
+set_property -dict {LOC P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
+set_property -dict {LOC P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
+set_property -dict {LOC P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
+
+# UART
+set_property -dict {LOC Y23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd]
+set_property -dict {LOC Y20 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
+
+# Gigabit Ethernet RGMII PHY
+set_property -dict {LOC AG10 IOSTANDARD LVCMOS15} [get_ports phy_rx_clk]
+set_property -dict {LOC AJ14 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[0]}]
+set_property -dict {LOC AH14 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[1]}]
+set_property -dict {LOC AK13 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[2]}]
+set_property -dict {LOC AJ13 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[3]}]
+set_property -dict {LOC AH11 IOSTANDARD LVCMOS15} [get_ports phy_rx_ctl]
+set_property -dict {LOC AE10 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports phy_tx_clk]
+set_property -dict {LOC AJ12 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}]
+set_property -dict {LOC AK11 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}]
+set_property -dict {LOC AJ11 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}]
+set_property -dict {LOC AK10 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}]
+set_property -dict {LOC AK14 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports phy_tx_ctl]
+set_property -dict {LOC AH24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
+set_property -dict {LOC AK16 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
+set_property -dict {LOC AK15 IOSTANDARD LVCMOS18} [get_ports phy_pme_n]
+set_property -dict {LOC AG12 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
+set_property -dict {LOC AF12 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
+
+create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
+set_clock_groups -asynchronous -group [get_clocks phy_rx_clk -include_generated_clocks]
+

example/Genesys2/fpga/fpga/Makefile

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+
+# FPGA settings
+FPGA_PART = xc7k325tffg900-2
+FPGA_TOP = fpga
+FPGA_ARCH = kintex7
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += lib/eth/rtl/iddr.v
+SYN_FILES += lib/eth/rtl/oddr.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_in.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_out.v
+SYN_FILES += lib/eth/rtl/rgmii_phy_if.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g.v
+SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
+SYN_FILES += lib/eth/rtl/udp.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx.v
+SYN_FILES += lib/eth/rtl/ip_complete.v
+SYN_FILES += lib/eth/rtl/ip.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += eth.xdc
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	djtgcfg prog -d Genesys2 --index 0 --file $(FPGA_TOP).bit
+

example/Genesys2/fpga/fpga/generate_bit_iodelay.tcl

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+open_project fpga.xpr
+open_run impl_1
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
+write_bitstream -force fpga.bit
+exit

example/Genesys2/fpga/lib/eth

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+../../../../