merged changes in axis

alexforencich · Jun 3, 2021 · 846183b · 846183b
2 parents 0512664 + 4fa3870
commit 846183b
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Showing 34 changed files with 185 additions and 135 deletions.
diff --git a/lib/axis/rtl/arbiter.v b/lib/axis/rtl/arbiter.v
@@ -1,6 +1,6 @@
 /*
 
-Copyright (c) 2014-2018 Alex Forencich
+Copyright (c) 2014-2021 Alex Forencich
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal
@@ -32,12 +32,14 @@ THE SOFTWARE.
 module arbiter #
 (
     parameter PORTS = 4,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter TYPE = "PRIORITY",
-    // block type: "NONE", "REQUEST", "ACKNOWLEDGE"
-    parameter BLOCK = "NONE",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "LOW"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 0,
+    // blocking arbiter enable
+    parameter ARB_BLOCK = 0,
+    // block on acknowledge assert when nonzero, request deassert when 0
+    parameter ARB_BLOCK_ACK = 1,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 0
 )
 (
     input  wire                     clk,
@@ -65,7 +67,7 @@ wire [PORTS-1:0] request_mask;
 
 priority_encoder #(
     .WIDTH(PORTS),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 priority_encoder_inst (
     .input_unencoded(request),
@@ -82,7 +84,7 @@ wire [PORTS-1:0] masked_request_mask;
 
 priority_encoder #(
     .WIDTH(PORTS),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 priority_encoder_masked (
     .input_unencoded(request & mask_reg),
@@ -97,41 +99,41 @@ always @* begin
     grant_encoded_next = 0;
     mask_next = mask_reg;
 
-    if (BLOCK == "REQUEST" && grant_reg & request) begin
+    if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin
         // granted request still asserted; hold it
         grant_valid_next = grant_valid_reg;
         grant_next = grant_reg;
         grant_encoded_next = grant_encoded_reg;
-    end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
+    end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin
         // granted request not yet acknowledged; hold it
         grant_valid_next = grant_valid_reg;
         grant_next = grant_reg;
         grant_encoded_next = grant_encoded_reg;
     end else if (request_valid) begin
-        if (TYPE == "PRIORITY") begin
-            grant_valid_next = 1;
-            grant_next = request_mask;
-            grant_encoded_next = request_index;
-        end else if (TYPE == "ROUND_ROBIN") begin
+        if (ARB_TYPE_ROUND_ROBIN) begin
             if (masked_request_valid) begin
                 grant_valid_next = 1;
                 grant_next = masked_request_mask;
                 grant_encoded_next = masked_request_index;
-                if (LSB_PRIORITY == "LOW") begin
-                    mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
-                end else begin
+                if (ARB_LSB_HIGH_PRIORITY) begin
                     mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
+                end else begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
                 end
             end else begin
                 grant_valid_next = 1;
                 grant_next = request_mask;
                 grant_encoded_next = request_index;
-                if (LSB_PRIORITY == "LOW") begin
-                    mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
-                end else begin
+                if (ARB_LSB_HIGH_PRIORITY) begin
                     mask_next = {PORTS{1'b1}} << (request_index + 1);
+                end else begin
+                    mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
                 end
             end
+        end else begin
+            grant_valid_next = 1;
+            grant_next = request_mask;
+            grant_encoded_next = request_index;
         end
     end
 end

diff --git a/lib/axis/rtl/axis_arb_mux.v b/lib/axis/rtl/axis_arb_mux.v
@@ -51,10 +51,10 @@ module axis_arb_mux #
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "PRIORITY",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 0,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1
 )
 (
     input  wire                          clk,
@@ -119,9 +119,10 @@ wire [USER_WIDTH-1:0] current_s_tuser  = s_axis_tuser[grant_encoded*USER_WIDTH +
 // arbiter instance
 arbiter #(
     .PORTS(S_COUNT),
-    .TYPE(ARB_TYPE),
-    .BLOCK("ACKNOWLEDGE"),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_BLOCK(1),
+    .ARB_BLOCK_ACK(1),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 arb_inst (
     .clk(clk),

diff --git a/lib/axis/rtl/axis_arb_mux_wrap.py b/lib/axis/rtl/axis_arb_mux_wrap.py
@@ -86,10 +86,10 @@ def generate(ports=4, name=None, output=None):
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "PRIORITY",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 0,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1
 )
 (
     input  wire                  clk,
@@ -132,8 +132,8 @@ def generate(ports=4, name=None, output=None):
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 axis_arb_mux_inst (
     .clk(clk),

diff --git a/lib/axis/rtl/axis_ram_switch.v b/lib/axis/rtl/axis_ram_switch.v
@@ -90,10 +90,10 @@ module axis_ram_switch #
     // Interface connection control
     // M_COUNT concatenated fields of S_COUNT bits
     parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "ROUND_ROBIN",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH",
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 1,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1,
     // RAM read data output pipeline stages
     parameter RAM_PIPELINE = 2
 )
@@ -263,9 +263,9 @@ if (S_COUNT > 1) begin
 
     arbiter #(
         .PORTS(S_COUNT),
-        .TYPE("ROUND_ROBIN"),
-        .BLOCK("NONE"),
-        .LSB_PRIORITY("HIGH")
+        .ARB_TYPE_ROUND_ROBIN(1),
+        .ARB_BLOCK(0),
+        .ARB_LSB_HIGH_PRIORITY(1)
     )
     ram_write_arb_inst (
         .clk(clk),
@@ -299,9 +299,9 @@ if (M_COUNT > 1) begin
 
     arbiter #(
         .PORTS(M_COUNT),
-        .TYPE("ROUND_ROBIN"),
-        .BLOCK("NONE"),
-        .LSB_PRIORITY("HIGH")
+        .ARB_TYPE_ROUND_ROBIN(1),
+        .ARB_BLOCK(0),
+        .ARB_LSB_HIGH_PRIORITY(1)
     )
     ram_read_arb_inst (
         .clk(clk),
@@ -483,9 +483,10 @@ generate
 
         arbiter #(
             .PORTS(M_COUNT),
-            .TYPE(ARB_TYPE),
-            .BLOCK("ACKNOWLEDGE"),
-            .LSB_PRIORITY(LSB_PRIORITY)
+            .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
         )
         cmd_status_arb_inst (
             .clk(clk),
@@ -802,9 +803,10 @@ generate
 
         arbiter #(
             .PORTS(S_COUNT),
-            .TYPE(ARB_TYPE),
-            .BLOCK("ACKNOWLEDGE"),
-            .LSB_PRIORITY(LSB_PRIORITY)
+            .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
         )
         cmd_arb_inst (
             .clk(clk),

diff --git a/lib/axis/rtl/axis_ram_switch_wrap.py b/lib/axis/rtl/axis_ram_switch_wrap.py
@@ -126,10 +126,10 @@ def generate(ports=4, name=None, output=None):
     // Interface connection control
     parameter M{{'%02d'%p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
 {%- endfor %}
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "ROUND_ROBIN",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH",
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 1,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1,
     // RAM read data output pipeline stages
     parameter RAM_PIPELINE = 2
 )
@@ -204,8 +204,8 @@ def generate(ports=4, name=None, output=None):
     .M_BASE({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_BASE){% if not loop.last %}, {% endif %}{% endfor %} }),
     .M_TOP({ {% for p in range(n-1,-1,-1) %}w_dw(M{{'%02d'%p}}_TOP){% if not loop.last %}, {% endif %}{% endfor %} }),
     .M_CONNECT({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT){% if not loop.last %}, {% endif %}{% endfor %} }),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY),
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY),
     .RAM_PIPELINE(RAM_PIPELINE)
 )
 axis_ram_switch_inst (

diff --git a/lib/axis/rtl/axis_switch.v b/lib/axis/rtl/axis_switch.v
@@ -71,10 +71,10 @@ module axis_switch #
     // Output interface register type
     // 0 to bypass, 1 for simple buffer, 2 for skid buffer
     parameter M_REG_TYPE = 2,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "ROUND_ROBIN",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 1,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1
 )
 (
     input  wire                   clk,
@@ -298,9 +298,10 @@ generate
 
         arbiter #(
             .PORTS(S_COUNT),
-            .TYPE(ARB_TYPE),
-            .BLOCK("ACKNOWLEDGE"),
-            .LSB_PRIORITY(LSB_PRIORITY)
+            .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
         )
         arb_inst (
             .clk(clk),

diff --git a/lib/axis/rtl/axis_switch_wrap.py b/lib/axis/rtl/axis_switch_wrap.py
@@ -107,10 +107,10 @@ def generate(ports=4, name=None, output=None):
     // Output interface register type
     // 0 to bypass, 1 for simple buffer, 2 for skid buffer
     parameter M_REG_TYPE = 2,
-    // arbitration type: "PRIORITY" or "ROUND_ROBIN"
-    parameter ARB_TYPE = "ROUND_ROBIN",
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    // select round robin arbitration
+    parameter ARB_TYPE_ROUND_ROBIN = 1,
+    // LSB priority selection
+    parameter ARB_LSB_HIGH_PRIORITY = 1
 )
 (
     input  wire                  clk,
@@ -169,8 +169,8 @@ def generate(ports=4, name=None, output=None):
     .M_CONNECT({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT){% if not loop.last %}, {% endif %}{% endfor %} }),
     .S_REG_TYPE(S_REG_TYPE),
     .M_REG_TYPE(M_REG_TYPE),
-    .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
+    .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
 )
 axis_switch_inst (
     .clk(clk),

diff --git a/lib/axis/rtl/priority_encoder.v b/lib/axis/rtl/priority_encoder.v
@@ -1,6 +1,6 @@
 /*
 
-Copyright (c) 2014-2018 Alex Forencich
+Copyright (c) 2014-2021 Alex Forencich
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal
@@ -32,8 +32,8 @@ THE SOFTWARE.
 module priority_encoder #
 (
     parameter WIDTH = 4,
-    // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "LOW"
+    // LSB priority selection
+    parameter LSB_HIGH_PRIORITY = 0
 )
 (
     input  wire [WIDTH-1:0]         input_unencoded,
@@ -57,21 +57,25 @@ generate
     // process input bits; generate valid bit and encoded bit for each pair
     for (n = 0; n < W/2; n = n + 1) begin : loop_in
         assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
-        if (LSB_PRIORITY == "LOW") begin
-            assign stage_enc[0][n] = input_padded[n*2+1];
-        end else begin
+        if (LSB_HIGH_PRIORITY) begin
+            // bit 0 is highest priority
             assign stage_enc[0][n] = !input_padded[n*2+0];
+        end else begin
+            // bit 0 is lowest priority
+            assign stage_enc[0][n] = input_padded[n*2+1];
         end
     end
 
     // compress down to single valid bit and encoded bus
     for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
         for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
             assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
-            if (LSB_PRIORITY == "LOW") begin
-                assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
-            end else begin
+            if (LSB_HIGH_PRIORITY) begin
+                // bit 0 is highest priority
                 assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
+            end else begin
+                // bit 0 is lowest priority
+                assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
             end
         end
     end

diff --git a/lib/axis/tb/axis_arb_mux/Makefile b/lib/axis/tb/axis_arb_mux/Makefile
@@ -47,6 +47,8 @@ export PARAM_DEST_ENABLE ?= 1
 export PARAM_DEST_WIDTH ?= 8
 export PARAM_USER_ENABLE ?= 1
 export PARAM_USER_WIDTH ?= 1
+export PARAM_ARB_TYPE_ROUND_ROBIN ?= 0
+export PARAM_ARB_LSB_HIGH_PRIORITY ?= 1
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst
@@ -60,6 +62,8 @@ ifeq ($(SIM), icarus)
 	COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH)
 	COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE)
 	COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).ARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
+	COMPILE_ARGS += -P $(TOPLEVEL).ARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
 
 	ifeq ($(WAVES), 1)
 		VERILOG_SOURCES += iverilog_dump.v
@@ -77,6 +81,8 @@ else ifeq ($(SIM), verilator)
 	COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH)
 	COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE)
 	COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH)
+	COMPILE_ARGS += -GARB_TYPE_ROUND_ROBIN=$(PARAM_ARB_TYPE_ROUND_ROBIN)
+	COMPILE_ARGS += -GARB_LSB_HIGH_PRIORITY=$(PARAM_ARB_LSB_HIGH_PRIORITY)
 
 	ifeq ($(WAVES), 1)
 		COMPILE_ARGS += --trace-fst