Enable overtemp shutdown in constraints files

Signed-off-by: Alex Forencich <[email protected]>
alexforencich · Jul 22, 2023 · 5d349c9 · 5d349c9
1 parent f4a8561
commit 5d349c9
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Showing 19 changed files with 47 additions and 28 deletions.
diff --git a/example/AU200/fpga_25g/fpga.xdc b/example/AU200/fpga_25g/fpga.xdc
@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 160
 

diff --git a/example/AU250/fpga_25g/fpga.xdc b/example/AU250/fpga_25g/fpga.xdc
@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 160
 

diff --git a/example/AU280/fpga_25g/fpga.xdc b/example/AU280/fpga_25g/fpga.xdc
@@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 160
 

diff --git a/example/AU50/fpga_25g/fpga.xdc b/example/AU50/fpga_25g/fpga.xdc
@@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 63
 

diff --git a/example/Arty/fpga/fpga.xdc b/example/Arty/fpga/fpga.xdc
@@ -2,11 +2,12 @@
 # part: xc7a35t-csg324-1
 
 # General configuration
-set_property CFGBVS VCCO                     [current_design]
-set_property CONFIG_VOLTAGE 3.3              [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
-set_property BITSTREAM.CONFIG.CONFIGRATE 50  [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CFGBVS VCCO                               [current_design]
+set_property CONFIG_VOLTAGE 3.3                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50            [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz clock
 set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk]

diff --git a/example/ExaNIC_X10/fpga/fpga.xdc b/example/ExaNIC_X10/fpga/fpga.xdc
@@ -2,13 +2,14 @@
 # part: xcku035-fbva676-2-e
 
 # General configuration
-set_property CFGBVS GND                           [current_design]
-set_property CONFIG_VOLTAGE 1.8                   [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true      [current_design]
-set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup    [current_design]
-set_property BITSTREAM.CONFIG.CONFIGRATE 50       [current_design]
-set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design]
-set_property CONFIG_MODE BPI16                    [current_design]
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup         [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50            [current_design]
+set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2      [current_design]
+set_property CONFIG_MODE BPI16                         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz system clock
 set_property -dict {LOC D18  IOSTANDARD LVDS} [get_ports clk_100mhz_p]

diff --git a/example/HTG9200/fpga_25g/fpga.xdc b/example/HTG9200/fpga_25g/fpga.xdc
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # DDR4 clocks from U5 (200 MHz)

diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # DDR4 clocks from U5 (200 MHz)

diff --git a/example/KC705/fpga_gmii/fpga.xdc b/example/KC705/fpga_gmii/fpga.xdc
@@ -2,9 +2,10 @@
 # part: xc7k325tffg900-2
 
 # General configuration
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 2.5 [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+set_property CFGBVS VCCO                               [current_design]
+set_property CONFIG_VOLTAGE 2.5                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 200 MHz

diff --git a/example/KC705/fpga_rgmii/fpga.xdc b/example/KC705/fpga_rgmii/fpga.xdc
@@ -2,9 +2,10 @@
 # part: xc7k325tffg900-2
 
 # General configuration
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 2.5 [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+set_property CFGBVS VCCO                               [current_design]
+set_property CONFIG_VOLTAGE 2.5                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 200 MHz

diff --git a/example/KC705/fpga_sgmii/fpga.xdc b/example/KC705/fpga_sgmii/fpga.xdc
@@ -2,9 +2,10 @@
 # part: xc7k325tffg900-2
 
 # General configuration
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 2.5 [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+set_property CFGBVS VCCO                               [current_design]
+set_property CONFIG_VOLTAGE 2.5                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 200 MHz

diff --git a/example/NetFPGA_SUME/fpga/fpga.xdc b/example/NetFPGA_SUME/fpga/fpga.xdc
@@ -2,10 +2,11 @@
 # part: xc7vx690tffg1761-3
 
 # General configuration
-set_property CFGBVS GND                           [current_design]
-set_property CONFIG_VOLTAGE 1.8                   [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true      [current_design]
-set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup    [current_design]
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 200 MHz system clock
 set_property -dict {LOC H19  IOSTANDARD LVDS} [get_ports clk_200mhz_p]

diff --git a/example/NexysVideo/fpga/fpga.xdc b/example/NexysVideo/fpga/fpga.xdc
@@ -2,9 +2,10 @@
 # part: xc7a200tsbg484-1
 
 # General configuration
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+set_property CFGBVS VCCO                               [current_design]
+set_property CONFIG_VOLTAGE 3.3                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz clock
 set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]

diff --git a/example/VCU108/fpga_10g/fpga.xdc b/example/VCU108/fpga_10g/fpga.xdc
@@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
 set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1      [current_design]
 set_property CONFIG_MODE BPI16                         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

diff --git a/example/VCU108/fpga_1g/fpga.xdc b/example/VCU108/fpga_1g/fpga.xdc
@@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
 set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1      [current_design]
 set_property CONFIG_MODE BPI16                         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

diff --git a/example/VCU118/fpga_1g/fpga.xdc b/example/VCU118/fpga_1g/fpga.xdc
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

diff --git a/example/VCU118/fpga_25g/fpga.xdc b/example/VCU118/fpga_25g/fpga.xdc
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

diff --git a/example/VCU1525/fpga_25g/fpga.xdc b/example/VCU1525/fpga_25g/fpga.xdc
@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz (DDR 0)