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Deprecate RTLIL::id2cstr() #5356

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2 changes: 1 addition & 1 deletion backends/cxxrtl/cxxrtl_backend.cc
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Expand Up @@ -3433,7 +3433,7 @@ struct CxxrtlWorker {

if (!design->selected_whole_module(module))
if (design->selected_module(module))
log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
log_cmd_error("Can't handle partially selected module `%s'!\n", log_id(module->name));
if (!design->selected_module(module))
continue;

Expand Down
14 changes: 7 additions & 7 deletions docs/source/code_examples/functional/dummy.cc
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Expand Up @@ -24,19 +24,19 @@ struct FunctionalDummyBackend : public Backend {

// write node functions
for (auto node : ir)
*f << " assign " << id2cstr(node.name())
*f << " assign " << log_id(node.name())
<< " = " << node.to_string() << "\n";
*f << "\n";

// write outputs and next state
for (auto output : ir.outputs())
*f << " " << id2cstr(output->kind)
<< " " << id2cstr(output->name)
<< " = " << id2cstr(output->value().name()) << "\n";
*f << " " << log_id(output->kind)
<< " " << log_id(output->name)
<< " = " << log_id(output->value().name()) << "\n";
for (auto state : ir.states())
*f << " " << id2cstr(state->kind)
<< " " << id2cstr(state->name)
<< " = " << id2cstr(state->next_value().name()) << "\n";
*f << " " << log_id(state->kind)
<< " " << log_id(state->name)
<< " = " << log_id(state->next_value().name()) << "\n";
}
}
} FunctionalDummyBackend;
Expand Down
6 changes: 3 additions & 3 deletions docs/source/code_examples/stubnets/stubnets.cc
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Expand Up @@ -27,7 +27,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// count output lines for this module (needed only for summary output at the end)
int line_count = 0;

log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
log("Looking for stub wires in module %s:\n", log_id(module->name));

// For all ports on all cells
for (auto &cell_iter : module->cells_)
Expand Down Expand Up @@ -74,11 +74,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// report stub bits and/or stub wires, don't report single bits
// if called with report_bits set to false.
if (GetSize(stub_bits) == GetSize(sig)) {
log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
log(" found stub wire: %s\n", log_id(wire->name));
} else {
if (!report_bits)
continue;
log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name));
log(" found wire with stub bits: %s [", log_id(wire->name));
for (int bit : stub_bits)
log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
log("]\n");
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2 changes: 1 addition & 1 deletion docs/source/yosys_internals/extending_yosys/extensions.rst
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Expand Up @@ -231,7 +231,7 @@ Use ``log_error()`` to report a non-recoverable error:

if (design->modules.count(module->name) != 0)
log_error("A module with the name %s already exists!\n",
RTLIL::id2cstr(module->name));
log_id(module->name));

Use ``log_cmd_error()`` to report a recoverable error:

Expand Down
2 changes: 1 addition & 1 deletion docs/source/yosys_internals/extending_yosys/functional_ir.rst
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Expand Up @@ -181,7 +181,7 @@ pointer ``f`` to the output file, or stdout if none is given.

For this minimal example all we are doing is printing out each node. The
``node.name()`` method returns an ``RTLIL::IdString``, which we convert for
printing with ``id2cstr()``. Then, to print the function of the node, we use
printing with ``log_id()``. Then, to print the function of the node, we use
``node.to_string()`` which gives us a string of the form ``function(args)``. The
``function`` part is the result of ``Functional::IR::fn_to_string(node.fn())``;
while ``args`` is the zero or more arguments passed to the function, most
Expand Down
4 changes: 2 additions & 2 deletions frontends/verific/verific.cc
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Expand Up @@ -1478,10 +1478,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
design->add(module);

if (is_blackbox(nl)) {
log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
log("Importing blackbox module %s.\n", log_id(module->name));
module->set_bool_attribute(ID::blackbox);
} else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
log("Importing module %s.\n", log_id(module->name));
}
import_attributes(module->attributes, nl, nl);
if (module->name.isPublic())
Expand Down
6 changes: 3 additions & 3 deletions kernel/rtlil.cc
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Expand Up @@ -1484,7 +1484,7 @@ void RTLIL::Module::makeblackbox()

void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
{
log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name));
log_error("Class doesn't support expand_interfaces (module: `%s')!\n", log_id(name));
}

bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
Expand All @@ -1496,15 +1496,15 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString
{
if (mayfail)
return RTLIL::IdString();
log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
log_error("Module `%s' is used with parameters but is not parametric!\n", log_id(name));
}


RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
{
if (mayfail)
return RTLIL::IdString();
log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
log_error("Module `%s' is used with parameters but is not parametric!\n", log_id(name));
}

size_t RTLIL::Module::count_id(const RTLIL::IdString& id)
Expand Down
1 change: 1 addition & 0 deletions kernel/rtlil.h
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Expand Up @@ -580,6 +580,7 @@ namespace RTLIL {
return unescape_id(str.str());
}

[[deprecated("Use log_id() instead")]]
static inline const char *id2cstr(const RTLIL::IdString &str) {
return log_id(str);
}
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6 changes: 3 additions & 3 deletions passes/cmds/scc.cc
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Expand Up @@ -87,7 +87,7 @@ struct SccWorker
RTLIL::Cell *c = cellStack.back();
cellStack.pop_back();
cellsOnStack.erase(c);
log(" %s", RTLIL::id2cstr(c->name));
log(" %s", log_id(c->name));
cell2scc[c] = sccList.size();
scc.insert(c);
}
Expand Down Expand Up @@ -201,7 +201,7 @@ struct SccWorker
if (!nofeedbackMode && cellToNextCell[cell].count(cell)) {
log("Found an SCC:");
pool<RTLIL::Cell*> scc;
log(" %s", RTLIL::id2cstr(cell->name));
log(" %s", log_id(cell->name));
cell2scc[cell] = sccList.size();
scc.insert(cell);
sccList.push_back(scc);
Expand All @@ -221,7 +221,7 @@ struct SccWorker
run(cell, 0, maxDepth);
}

log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name));
log("Found %d SCCs in module %s.\n", int(sccList.size()), log_id(module->name));
}

void select(RTLIL::Selection &sel)
Expand Down
18 changes: 8 additions & 10 deletions passes/cmds/select.cc
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Expand Up @@ -25,8 +25,6 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

using RTLIL::id2cstr;

static std::vector<RTLIL::Selection> work_stack;

static bool match_ids(RTLIL::IdString id, const std::string &pattern)
Expand Down Expand Up @@ -1022,9 +1020,9 @@ static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::S
for (auto mod : design->all_selected_modules())
{
if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name));
desc += stringf("%s\n", log_id(mod->name));
for (auto it : mod->selected_members())
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it->name));
desc += stringf("%s/%s\n", log_id(mod->name), log_id(it->name));
}
if (push_selection) design->pop_selection();
return desc;
Expand Down Expand Up @@ -1414,7 +1412,7 @@ struct SelectPass : public Pass {
if (arg == "-module" && argidx+1 < args.size()) {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (design->module(mod_name) == nullptr)
log_cmd_error("No such module: %s\n", id2cstr(mod_name));
log_cmd_error("No such module: %s\n", log_id(mod_name));
design->selected_active_module = mod_name.str();
got_module = true;
continue;
Expand Down Expand Up @@ -1527,10 +1525,10 @@ struct SelectPass : public Pass {
for (auto mod : design->all_selected_modules())
{
if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name));
log("%s\n", log_id(mod->name));
if (!list_mod_mode)
for (auto it : mod->selected_members())
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it->name))
LOG_OBJECT("%s/%s\n", log_id(mod->name), log_id(it->name))
}
if (count_mode)
{
Expand Down Expand Up @@ -1654,10 +1652,10 @@ struct SelectPass : public Pass {
if (sel.full_selection)
log("*\n");
for (auto &it : sel.selected_modules)
log("%s\n", id2cstr(it));
log("%s\n", log_id(it));
for (auto &it : sel.selected_members)
for (auto &it2 : it.second)
log("%s/%s\n", id2cstr(it.first), id2cstr(it2));
log("%s/%s\n", log_id(it.first), log_id(it2));
return;
}

Expand Down Expand Up @@ -1779,7 +1777,7 @@ static void log_matches(const char *title, Module *module, const T &list)
log("\n%d %s:\n", int(matches.size()), title);
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
for (auto id : matches)
log(" %s\n", RTLIL::id2cstr(id));
log(" %s\n", log_id(id));
}
}

Expand Down
4 changes: 2 additions & 2 deletions passes/cmds/test_select.cc
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Expand Up @@ -144,10 +144,10 @@ struct TestSelectPass : public Pass {

for (auto *mod : sub_sel) {
if (mod->is_selected_whole()) {
log_debug(" Adding %s.\n", id2cstr(mod->name));
log_debug(" Adding %s.\n", log_id(mod->name));
selected_modules.insert(mod->name);
} else for (auto *memb : mod->selected_members()) {
log_debug(" Adding %s.%s.\n", id2cstr(mod->name), id2cstr(memb->name));
log_debug(" Adding %s.%s.\n", log_id(mod->name), log_id(memb->name));
selected_members[mod->name].insert(memb);
}
}
Expand Down
4 changes: 2 additions & 2 deletions passes/equiv/equiv_make.cc
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Expand Up @@ -284,11 +284,11 @@ struct EquivMakeWorker

for (int i = 0; i < wire->width; i++) {
if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i);
log(" Skipping signal bit %s [%d]: undriven on gold side.\n", log_id(gold_wire->name), i);
continue;
}
if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
log(" Skipping signal bit %s [%d]: undriven on gate side.\n", log_id(gate_wire->name), i);
continue;
}
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
Expand Down
2 changes: 1 addition & 1 deletion passes/fsm/fsm_detect.cc
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Expand Up @@ -61,7 +61,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, poo

if (recursion_monitor.count(cellport.first)) {
log_warning("logic loop in mux tree at signal %s in module %s.\n",
log_signal(sig), RTLIL::id2cstr(module->name));
log_signal(sig), log_id(module->name));
goto ret_false;
}

Expand Down
28 changes: 14 additions & 14 deletions passes/hierarchy/hierarchy.cc
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Expand Up @@ -87,7 +87,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
if (decl.index > 0) {
portwidths[decl.portname] = max(portwidths[decl.portname], 1);
portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname));
log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, log_id(decl.portname));
if (indices.count(decl.index) > ports.size())
log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size()));
if (indices.count(decl.index) == 0)
Expand All @@ -108,10 +108,10 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
indices.erase(d.index);
ports[d.index-1] = d;
portwidths[d.portname] = max(portwidths[d.portname], 1);
log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname));
log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, log_id(d.portname));
goto found_matching_decl;
}
log_error("Can't match port %s.\n", RTLIL::id2cstr(portname));
log_error("Can't match port %s.\n", log_id(portname));
found_matching_decl:;
portnames.erase(portname);
}
Expand All @@ -133,9 +133,9 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
mod->fixup_ports();

for (auto &para : parameters)
log(" ignoring parameter %s.\n", RTLIL::id2cstr(para));
log(" ignoring parameter %s.\n", log_id(para));

log(" module %s created.\n", RTLIL::id2cstr(mod->name));
log(" module %s created.\n", log_id(mod->name));
}
}

Expand Down Expand Up @@ -570,7 +570,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
int idx = it.second.first, num = it.second.second;

if (design->module(cell->type) == nullptr)
log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_error("Array cell `%s.%s' of unknown type `%s'.\n", log_id(module->name), log_id(cell->name), log_id(cell->type));

RTLIL::Module *mod = design->module(cell->type);

Expand All @@ -586,12 +586,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
}
}
if (mod->wire(portname) == nullptr)
log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", log_id(module->name), log_id(cell->name), log_id(conn.first));
int port_size = mod->wire(portname)->width;
if (conn_size == port_size || conn_size == 0)
continue;
if (conn_size != port_size*num)
log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", log_id(module->name), log_id(cell->name), log_id(conn.first));
conn.second = conn.second.extract(port_size*idx, port_size);
}
}
Expand Down Expand Up @@ -1173,7 +1173,7 @@ struct HierarchyPass : public Pass {
if (read_id_num(p.first, &id)) {
if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) {
log(" Failed to map positional parameter %d of cell %s.%s (%s).\n",
id, RTLIL::id2cstr(mod->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
id, log_id(mod->name), log_id(cell->name), log_id(cell->type));
} else {
params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1]));
}
Expand All @@ -1195,15 +1195,15 @@ struct HierarchyPass : public Pass {
RTLIL::Module *module = work.first;
RTLIL::Cell *cell = work.second;
log("Mapping positional arguments of cell %s.%s (%s).\n",
RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_id(module->name), log_id(cell->name), log_id(cell->type));
dict<RTLIL::IdString, RTLIL::SigSpec> new_connections;
for (auto &conn : cell->connections()) {
int id;
if (read_id_num(conn.first, &id)) {
std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
if (pos_map.count(key) == 0) {
log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
id, log_id(module->name), log_id(cell->name), log_id(cell->type));
new_connections[conn.first] = conn.second;
} else
new_connections[pos_map.at(key)] = conn.second;
Expand Down Expand Up @@ -1237,7 +1237,7 @@ struct HierarchyPass : public Pass {

if (m == nullptr)
log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n",
RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_id(module->name), log_id(cell->name), log_id(cell->type));

// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
Expand Down Expand Up @@ -1266,11 +1266,11 @@ struct HierarchyPass : public Pass {

if (parent_wire == nullptr)
log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n",
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_id(wire->name), log_id(module->name), log_id(cell->name), log_id(cell->type));
if (parent_wire->width != wire->width)
log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n",
parent_wire->width, wire->width,
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_id(wire->name), log_id(module->name), log_id(cell->name), log_id(cell->type));
cell->setPort(wire->name, parent_wire);
}
cell->attributes.erase(ID::wildcard_port_conns);
Expand Down
2 changes: 0 additions & 2 deletions passes/opt/opt_clean.cc
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Expand Up @@ -29,8 +29,6 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

using RTLIL::id2cstr;

struct keep_cache_t
{
Design *design;
Expand Down
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