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Pull requests: YosysHQ/yosys

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Pull requests list

Update verilog_frontend.cc
#5102 opened May 7, 2025 by KrystalDelusion Loading…
rename: add -move-to-cell option in -wire mode
#5100 opened May 7, 2025 by jix Loading…
rtlil: enable single-bit vector wires
#5095 opened May 6, 2025 by widlarizer Loading…
cutpoint: Re-add whole module optimization
#5089 opened May 5, 2025 by KrystalDelusion Loading…
driver: add --no-version to suppress writing Yosys version merge-soon Merge: PR will be merged at the end of the next work day unless concerns are raised
#5086 opened May 5, 2025 by widlarizer Loading…
autoname: Check for potential overflow
#5081 opened May 1, 2025 by KrystalDelusion Loading…
Add muldiv_c peepopt
#5080 opened Apr 30, 2025 by akashlevy Loading…
Updates to bugpoint
#5068 opened Apr 28, 2025 by KrystalDelusion Draft
2 of 3 tasks
more detailed Stat command
#5054 opened Apr 23, 2025 by suisseWalter Draft
Updating test_cell
#5024 opened Apr 15, 2025 by KrystalDelusion Loading…
7 tasks done
dump: add --sorted flag
#5003 opened Apr 8, 2025 by widlarizer Loading…
QuickLogic DSPv2 support
#4932 opened Mar 11, 2025 by povik Draft
1 of 2 tasks
Add groups to command reference
#4860 opened Jan 20, 2025 by KrystalDelusion Loading…
ProTip! Exclude everything labeled bug with -label:bug.