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413 Open 1,279 Closed
413 Open 1,279 Closed
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Issues list

Support quoted strings as arguments to passes feature-request
#4511 opened Jul 26, 2024 by gussmith23
6
Autoname seems to get stuck in a loop and consume all the memory on the system pending-verification This issue is pending verification and/or reproduction
#4509 opened Jul 25, 2024 by QuantamHD
Add support/workaround for flattening inout port with tri-state signals feature-request
#4501 opened Jul 21, 2024 by Rodrigodd
5
yosys -sim hangs on multiple writes to the same memory address
#4496 opened Jul 18, 2024 by aiju
Any plans to add CDC linting? feature-request
#4493 opened Jul 16, 2024 by chili-chips-ba
9
Custom Yosys Passes Result in Faulty Synthesis and Simulation Errors pending-verification This issue is pending verification and/or reproduction
#4491 opened Jul 15, 2024 by LoSyTe
5
ABC: execution of command failed return code 139. ABC bug dependencies
#4473 opened Jul 2, 2024 by kareefardi
3
Can't build from 0.42 tarball pending-verification This issue is pending verification and/or reproduction
#4470 opened Jun 29, 2024 by spth
1
1
support error for Aggregate Initialization and Replication feature-request
#4462 opened Jun 18, 2024 by yelen103
1
CologneChip synthesis fails silently (simulation discrepancies) bug
#4457 opened Jun 15, 2024 by tarik-ibrahimovic
2
Feature Request: Add Support for Input Filelist Option feature-request
#4456 opened Jun 15, 2024 by tarik-ibrahimovic
8
IDES4_MEM gowin module is missing needs-info Issue needs more context/information in order to be resolved
#4453 opened Jun 13, 2024 by LaneaLucy
2
count_id(cell->name) == 0 failure ABC bug
#4451 opened Jun 13, 2024 by wyager
1
check-git-abc in Makefile for the first compile time pending-verification This issue is pending verification and/or reproduction
#4449 opened Jun 13, 2024 by nlwmode
4
Clean up uses of #if(n)def EMSCRIPTEN
#4438 opened Jun 10, 2024 by nakengelhardt
Ensuring smooth Yosys-to-Synlig compatability and tracking feature-request
#4436 opened Jun 9, 2024 by chili-chips-ba
13
Yosys Verilog Parsing Error: Unable to Synthesize After Reading File bug
#4427 opened Jun 4, 2024 by LoSyTe
1
2
formal: Produced traces make it look like asserts trigger a clock step too late pending-verification This issue is pending verification and/or reproduction
#4426 opened Jun 3, 2024 by NikLeberg
7
CXXRTL: >20x compile time regression with clang++-18 bug cxxrtl pending-verification This issue is pending verification and/or reproduction
#4419 opened May 27, 2024 by Wren6991
3
A topological loop is generated after using async2sync pending-verification This issue is pending verification and/or reproduction
#4414 opened May 24, 2024 by ZhiyuanYan
2
Yosys right shift error pending-verification This issue is pending verification and/or reproduction
#4413 opened May 24, 2024 by WeneneW
7
create a pip install package wheel for Windows feature-request
#4410 opened May 22, 2024 by eabase
4
Abnormal output pending-verification This issue is pending verification and/or reproduction
#4407 opened May 22, 2024 by WeneneW
1
make error 'abc' is not configured as a git submodule. pending-verification This issue is pending verification and/or reproduction
#4403 opened May 20, 2024 by Krishnakumarmohanraj
15
read_verilog doesn't respect signed keyword bug
#4402 opened May 18, 2024 by WeneneW
2
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