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480 Open 1,386 Closed
480 Open 1,386 Closed
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Issues list

Wide mux cells ($_MUX4_ et al) are incorrectly marked as evaluable pending-verification This issue is pending verification and/or reproduction
#5035 opened Apr 16, 2025 by KrystalDelusion
1
failure in yosys-abc with return code 134 pending-verification This issue is pending verification and/or reproduction
#5028 opened Apr 16, 2025 by Cronus-38
2
Liberty reader ignores copyrighted content bug fix pending PR with a fix is pending
#5027 opened Apr 15, 2025 by povik
1
Possibly incorrect non-blocking assignment in ecp5 cells_sim
#5026 opened Apr 15, 2025 by secworks
Add support for mapping arrays with global reset to memory_map
#5022 opened Apr 14, 2025 by nakengelhardt
@jix
AddressSanitizer issues pending-verification This issue is pending verification and/or reproduction
#5020 opened Apr 11, 2025 by KrystalDelusion
equiv_opt falsely claims equivalence on designs with different unknown modules bug
#5018 opened Apr 11, 2025 by widlarizer
@widlarizer
fsm_expand deleting design if state register is not initialised pending-verification This issue is pending verification and/or reproduction
#5014 opened Apr 10, 2025 by KelvinChung2000
1
Yosys not reporting non-existing files pending-verification This issue is pending verification and/or reproduction
#5013 opened Apr 10, 2025 by MrJake222
opt_mem pass is not respecting (* keep *) bug
#5010 opened Apr 9, 2025 by KelvinChung2000
1
Add annotations in CI for warnings in tests feature-request
#5007 opened Apr 9, 2025 by KrystalDelusion
Script errors should give a line number feature-request
#5006 opened Apr 9, 2025 by KrystalDelusion
Possible memory leak at CHECK pass pending-verification This issue is pending verification and/or reproduction
#5002 opened Apr 8, 2025 by RicardoLera
2
ANSI-style modules from write_verilog feature-request
#4993 opened Apr 6, 2025 by oscargus
ERROR: Assert sig_macc.count(n->y) == 0 failed occurs when multiple $add cells drive the same signal. pending-verification This issue is pending verification and/or reproduction
#4991 opened Apr 5, 2025 by sdjasj
2
Support wildcards across Liberty file consumers feature-request
#4990 opened Apr 4, 2025 by widlarizer
@widlarizer
Inconsistent 'x handling in opt_expr for muxes pending-verification This issue is pending verification and/or reproduction
#4988 opened Apr 3, 2025 by KrystalDelusion
ERROR: Assert 'signal_list[id1].bit.wire != nullptr' occurred during the synth_efinix pending-verification This issue is pending verification and/or reproduction
#4987 opened Apr 3, 2025 by sdjasj
8
A core dumped occurred during the synth_microchip process when executing the MICROCHIP_DSP pass. pending-verification This issue is pending verification and/or reproduction
#4985 opened Apr 3, 2025 by sdjasj
2
A core dump occurred during the synth_coolrunner2 process. pending-verification This issue is pending verification and/or reproduction
#4984 opened Apr 2, 2025 by sdjasj
2
An integer overflow occurred during the Executing AUTONAME pass. pending-verification This issue is pending verification and/or reproduction
#4983 opened Apr 2, 2025 by sdjasj
The synth_efinix synthesis process keeps Adding EN signal and does not terminate. bug
#4979 opened Apr 1, 2025 by sdjasj
1
muxcover pass stalls if $_MUX_ output is disconnected pending-verification This issue is pending verification and/or reproduction
#4978 opened Apr 1, 2025 by KrystalDelusion
2
yosys-abc: src/map/scl/sclLibUtil.c:77: void abc::Abc_SclHashCells(SC_Lib *): Assertion `*pPlace == -1' failed. ABC error handling Error handling and reporting
#4977 opened Mar 31, 2025 by oharboe
9
An infinite loop occurred in the log during the synth_greenpak4 process. bug
#4972 opened Mar 31, 2025 by sdjasj
2
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