OpenSTA verilog compatibility

[widlarizer]

OpenSTA's read_verilog command supports a limited subset of Verilog. With this PR, yosys should be able to consistently present a design including derived blackboxes of internal cells made public with. The usefulness of these code changes is yet to be determined so it's a draft for now

I'm adding to box_derive a mode named -apply which actually remaps instances of parametric modules to be instances of the new derived ones. I'm also adding a publish pass that escapes internal cell types to become valid identifiers. @povik does the -apply mode seem sensible?

• add tests
• discard cell parameters in box_derive -apply I ended up not using this but for my use case I'm contributing it anyway since it's well defined and tested. Removing the parameters could be done in a followup if necessary

[povik]

I'd rename the new option otherwise the box_derive changes look good to me

[widlarizer]

Ideally, I'd add

design -reset
read_verilog <<EOT
module top(input A, input B, output Y);
assign Y = A ^ B;
endmodule
EOT

select -assert-count 1 t:$xor
select -assert-count 0 t:\$xor
chtype -publish_icells
dump
select -assert-count 0 t:$xor
select -assert-count 1 t:\$xor

or similar to tests/techmap/techmap_chtype.ys. However, #5414