OpenSTA verilog compatibility #5197
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povik
reviewed
Jul 17, 2025
| } | ||
| } | ||
| public: | ||
| PublishPass() : Pass("publish", "publish private cell types") { } |
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I'd say this is a general name for a niche application. What about chtype -publish_icells?
| @@ -51,6 +51,9 @@ struct BoxDerivePass : Pass { | |||
| log(" replaces the internal Yosys naming scheme in which the names of derived\n"); | |||
| log(" modules start with '$paramod$')\n"); | |||
| log("\n"); | |||
| log(" -apply\n"); | |||
| log(" use the derived modules\n"); | |||
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OpenSTA's
read_verilogcommand supports a limited subset of Verilog. With this PR, yosys should be able to consistently present a design including derived blackboxes of internal cells made public with. The usefulness of these code changes is yet to be determined so it's a draft for nowI'm adding to
box_derivea mode named-applywhich actually remaps instances of parametric modules to be instances of the new derived ones. I'm also adding apublishpass that escapes internal cell types to become valid identifiers. @povik does the-applymode seem sensible?box_derive -apply