merged changes in eth

ucsdsysnet · Jan 15, 2024 · beb34f5 · beb34f5
2 parents 913394b + b22db1d
commit beb34f5
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diff --git a/.../example/Arista_7132LB/fpga_25g/README.md → .../eth/example/DCS7132LB/fpga_25g/README.md b/.../example/Arista_7132LB/fpga_25g/README.md → .../eth/example/DCS7132LB/fpga_25g/README.md
diff --git a/...e/Arista_7132LB/fpga_25g/common/vivado.mk → ...ample/DCS7132LB/fpga_25g/common/vivado.mk b/...e/Arista_7132LB/fpga_25g/common/vivado.mk → ...ample/DCS7132LB/fpga_25g/common/vivado.mk
diff --git a/...h/example/Arista_7132LB/fpga_25g/fpga.xdc → ...b/eth/example/DCS7132LB/fpga_25g/fpga.xdc b/...h/example/Arista_7132LB/fpga_25g/fpga.xdc → ...b/eth/example/DCS7132LB/fpga_25g/fpga.xdc
diff --git a/...mple/Arista_7132LB/fpga_25g/fpga/Makefile → .../example/DCS7132LB/fpga_25g/fpga/Makefile b/...mple/Arista_7132LB/fpga_25g/fpga/Makefile → .../example/DCS7132LB/fpga_25g/fpga/Makefile
diff --git a/...le/Arista_7132LB/fpga_25g/fpga/config.tcl → ...xample/DCS7132LB/fpga_25g/fpga/config.tcl b/...le/Arista_7132LB/fpga_25g/fpga/config.tcl → ...xample/DCS7132LB/fpga_25g/fpga/config.tcl
diff --git a/.../Arista_7132LB/fpga_25g/fpga_10g/Makefile → ...mple/DCS7132LB/fpga_25g/fpga_10g/Makefile b/.../Arista_7132LB/fpga_25g/fpga_10g/Makefile → ...mple/DCS7132LB/fpga_25g/fpga_10g/Makefile
diff --git a/...rista_7132LB/fpga_25g/fpga_10g/config.tcl → ...le/DCS7132LB/fpga_25g/fpga_10g/config.tcl b/...rista_7132LB/fpga_25g/fpga_10g/config.tcl → ...le/DCS7132LB/fpga_25g/fpga_10g/config.tcl
diff --git a/...Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl → ...ple/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl b/...Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl → ...ple/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl
diff --git a/...th/example/Arista_7132LB/fpga_25g/lib/eth → ...ib/eth/example/DCS7132LB/fpga_25g/lib/eth b/...th/example/Arista_7132LB/fpga_25g/lib/eth → ...ib/eth/example/DCS7132LB/fpga_25g/lib/eth
diff --git a/.../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v → .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/.../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v → .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
diff --git a/...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v → ...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v → ...132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
diff --git a/...example/Arista_7132LB/fpga_25g/rtl/fpga.v → ...eth/example/DCS7132LB/fpga_25g/rtl/fpga.v b/...example/Arista_7132LB/fpga_25g/rtl/fpga.v → ...eth/example/DCS7132LB/fpga_25g/rtl/fpga.v
diff --git a/...le/Arista_7132LB/fpga_25g/rtl/fpga_core.v → ...xample/DCS7132LB/fpga_25g/rtl/fpga_core.v b/...le/Arista_7132LB/fpga_25g/rtl/fpga_core.v → ...xample/DCS7132LB/fpga_25g/rtl/fpga_core.v
diff --git a/.../Arista_7132LB/fpga_25g/rtl/sync_signal.v → ...mple/DCS7132LB/fpga_25g/rtl/sync_signal.v b/.../Arista_7132LB/fpga_25g/rtl/sync_signal.v → ...mple/DCS7132LB/fpga_25g/rtl/sync_signal.v
diff --git a/...sta_7132LB/fpga_25g/tb/fpga_core/Makefile → .../DCS7132LB/fpga_25g/tb/fpga_core/Makefile b/...sta_7132LB/fpga_25g/tb/fpga_core/Makefile → .../DCS7132LB/fpga_25g/tb/fpga_core/Makefile
diff --git a/...B/fpga_25g/tb/fpga_core/test_fpga_core.py → ...B/fpga_25g/tb/fpga_core/test_fpga_core.py b/...B/fpga_25g/tb/fpga_core/test_fpga_core.py → ...B/fpga_25g/tb/fpga_core/test_fpga_core.py
diff --git a/...LB/fpga_25g/tb/fpga_core/test_fpga_core.v → ...LB/fpga_25g/tb/fpga_core/test_fpga_core.v b/...LB/fpga_25g/tb/fpga_core/test_fpga_core.v → ...LB/fpga_25g/tb/fpga_core/test_fpga_core.v
diff --git a/fpga/lib/eth/rtl/axis_baser_tx_64.v b/fpga/lib/eth/rtl/axis_baser_tx_64.v
@@ -212,9 +212,8 @@ reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
 reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
 reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next;
 
-reg [31:0] crc_state = 32'hFFFFFFFF;
-
-wire [31:0] crc_next[7:0];
+reg [31:0] crc_state_reg[7:0];
+wire [31:0] crc_state_next[7:0];
 
 reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
 reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
@@ -252,9 +251,9 @@ generate
         )
         eth_crc (
             .data_in(s_tdata_reg[0 +: 8*(n+1)]),
-            .state_in(crc_state),
+            .state_in(crc_state_reg[7]),
             .data_out(),
-            .state_out(crc_next[n])
+            .state_out(crc_state_next[n])
         );
     end
 
@@ -288,57 +287,57 @@ end
 always @* begin
     casez (s_empty_reg)
         3'd7: begin
-            fcs_output_data_0 = {24'd0, ~crc_next[0][31:0], s_tdata_reg[7:0]};
+            fcs_output_data_0 = {24'd0, ~crc_state_next[0][31:0], s_tdata_reg[7:0]};
             fcs_output_data_1 = 64'd0;
             fcs_output_type_0 = OUTPUT_TYPE_TERM_5;
             fcs_output_type_1 = OUTPUT_TYPE_IDLE;
             ifg_offset = 8'd3;
         end
         3'd6: begin
-            fcs_output_data_0 = {16'd0, ~crc_next[1][31:0], s_tdata_reg[15:0]};
+            fcs_output_data_0 = {16'd0, ~crc_state_next[1][31:0], s_tdata_reg[15:0]};
             fcs_output_data_1 = 64'd0;
             fcs_output_type_0 = OUTPUT_TYPE_TERM_6;
             fcs_output_type_1 = OUTPUT_TYPE_IDLE;
             ifg_offset = 8'd2;
         end
         3'd5: begin
-            fcs_output_data_0 = {8'd0, ~crc_next[2][31:0], s_tdata_reg[23:0]};
+            fcs_output_data_0 = {8'd0, ~crc_state_next[2][31:0], s_tdata_reg[23:0]};
             fcs_output_data_1 = 64'd0;
             fcs_output_type_0 = OUTPUT_TYPE_TERM_7;
             fcs_output_type_1 = OUTPUT_TYPE_IDLE;
             ifg_offset = 8'd1;
         end
         3'd4: begin
-            fcs_output_data_0 = {~crc_next[3][31:0], s_tdata_reg[31:0]};
+            fcs_output_data_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]};
             fcs_output_data_1 = 64'd0;
             fcs_output_type_0 = OUTPUT_TYPE_DATA;
             fcs_output_type_1 = OUTPUT_TYPE_TERM_0;
             ifg_offset = 8'd8;
         end
         3'd3: begin
-            fcs_output_data_0 = {~crc_next[4][23:0], s_tdata_reg[39:0]};
-            fcs_output_data_1 = {56'd0, ~crc_next[4][31:24]};
+            fcs_output_data_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]};
+            fcs_output_data_1 = {56'd0, ~crc_state_reg[4][31:24]};
             fcs_output_type_0 = OUTPUT_TYPE_DATA;
             fcs_output_type_1 = OUTPUT_TYPE_TERM_1;
             ifg_offset = 8'd7;
         end
         3'd2: begin
-            fcs_output_data_0 = {~crc_next[5][15:0], s_tdata_reg[47:0]};
-            fcs_output_data_1 = {48'd0, ~crc_next[5][31:16]};
+            fcs_output_data_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]};
+            fcs_output_data_1 = {48'd0, ~crc_state_reg[5][31:16]};
             fcs_output_type_0 = OUTPUT_TYPE_DATA;
             fcs_output_type_1 = OUTPUT_TYPE_TERM_2;
             ifg_offset = 8'd6;
         end
         3'd1: begin
-            fcs_output_data_0 = {~crc_next[6][7:0], s_tdata_reg[55:0]};
-            fcs_output_data_1 = {40'd0, ~crc_next[6][31:8]};
+            fcs_output_data_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]};
+            fcs_output_data_1 = {40'd0, ~crc_state_reg[6][31:8]};
             fcs_output_type_0 = OUTPUT_TYPE_DATA;
             fcs_output_type_1 = OUTPUT_TYPE_TERM_3;
             ifg_offset = 8'd5;
         end
         3'd0: begin
             fcs_output_data_0 = s_tdata_reg;
-            fcs_output_data_1 = {32'd0, ~crc_next[7][31:0]};
+            fcs_output_data_1 = {32'd0, ~crc_state_reg[7][31:0]};
             fcs_output_type_0 = OUTPUT_TYPE_DATA;
             fcs_output_type_1 = OUTPUT_TYPE_TERM_4;
             ifg_offset = 8'd4;
@@ -531,6 +530,8 @@ always @* begin
             output_data_next = fcs_output_data_0;
             output_type_next = fcs_output_type_0;
 
+            update_crc = 1'b1;
+
             ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg;
             if (s_empty_reg <= 4) begin
                 state_next = STATE_FCS_2;
@@ -768,10 +769,20 @@ always @(posedge clk) begin
         end
     endcase
 
+    crc_state_reg[0] <= crc_state_next[0];
+    crc_state_reg[1] <= crc_state_next[1];
+    crc_state_reg[2] <= crc_state_next[2];
+    crc_state_reg[3] <= crc_state_next[3];
+    crc_state_reg[4] <= crc_state_next[4];
+    crc_state_reg[5] <= crc_state_next[5];
+    crc_state_reg[6] <= crc_state_next[6];
+
+    if (update_crc) begin
+        crc_state_reg[7] <= crc_state_next[7];
+    end
+
     if (reset_crc) begin
-        crc_state <= 32'hFFFFFFFF;
-    end else if (update_crc) begin
-        crc_state <= crc_next[7];
+        crc_state_reg[7] <= 32'hFFFFFFFF;
     end
 
     if (rst) begin

diff --git a/fpga/lib/eth/rtl/axis_xgmii_tx_32.v b/fpga/lib/eth/rtl/axis_xgmii_tx_32.v
@@ -155,9 +155,8 @@ reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
 reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
 reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
 
-reg [31:0] crc_state = 32'hFFFFFFFF;
-
-wire [31:0] crc_next[3:0];
+reg [31:0] crc_state_reg[3:0];
+wire [31:0] crc_state_next[3:0];
 
 reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next;
 reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next;
@@ -192,9 +191,9 @@ generate
         )
         eth_crc (
             .data_in(s_tdata_reg[0 +: 8*(n+1)]),
-            .state_in(crc_state),
+            .state_in(crc_state_reg[3]),
             .data_out(),
-            .state_out(crc_next[n])
+            .state_out(crc_state_next[n])
         );
     end
 
@@ -224,32 +223,32 @@ end
 always @* begin
     casez (s_empty_reg)
         2'd3: begin
-            fcs_output_txd_0 = {~crc_next[0][23:0], s_tdata_reg[7:0]};
-            fcs_output_txd_1 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_next[0][31:24]};
+            fcs_output_txd_0 = {~crc_state_next[0][23:0], s_tdata_reg[7:0]};
+            fcs_output_txd_1 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[0][31:24]};
             fcs_output_txc_0 = 4'b0000;
             fcs_output_txc_1 = 4'b1110;
             ifg_offset = 8'd3;
             extra_cycle = 1'b0;
         end
         2'd2: begin
-            fcs_output_txd_0 = {~crc_next[1][15:0], s_tdata_reg[15:0]};
-            fcs_output_txd_1 = {XGMII_IDLE, XGMII_TERM, ~crc_next[1][31:16]};
+            fcs_output_txd_0 = {~crc_state_next[1][15:0], s_tdata_reg[15:0]};
+            fcs_output_txd_1 = {XGMII_IDLE, XGMII_TERM, ~crc_state_reg[1][31:16]};
             fcs_output_txc_0 = 4'b0000;
             fcs_output_txc_1 = 4'b1100;
             ifg_offset = 8'd2;
             extra_cycle = 1'b0;
         end
         2'd1: begin
-            fcs_output_txd_0 = {~crc_next[2][7:0], s_tdata_reg[23:0]};
-            fcs_output_txd_1 = {XGMII_TERM, ~crc_next[2][31:8]};
+            fcs_output_txd_0 = {~crc_state_next[2][7:0], s_tdata_reg[23:0]};
+            fcs_output_txd_1 = {XGMII_TERM, ~crc_state_reg[2][31:8]};
             fcs_output_txc_0 = 4'b0000;
             fcs_output_txc_1 = 4'b1000;
             ifg_offset = 8'd1;
             extra_cycle = 1'b0;
         end
         2'd0: begin
             fcs_output_txd_0 = s_tdata_reg;
-            fcs_output_txd_1 = ~crc_next[3];
+            fcs_output_txd_1 = ~crc_state_reg[3];
             fcs_output_txc_0 = 4'b0000;
             fcs_output_txc_1 = 4'b0000;
             ifg_offset = 8'd4;
@@ -323,6 +322,7 @@ always @* begin
         end
         STATE_PREAMBLE: begin
             // send preamble
+            reset_crc = 1'b1;
 
             s_tdata_next = s_axis_tdata_masked;
             s_empty_next = keep2empty(s_axis_tkeep);
@@ -415,6 +415,8 @@ always @* begin
             xgmii_txd_next = fcs_output_txd_0;
             xgmii_txc_next = fcs_output_txc_0;
 
+            update_crc = 1'b1;
+
             ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + deficit_idle_count_reg;
             state_next = STATE_FCS_2;
         end
@@ -533,10 +535,16 @@ always @(posedge clk) begin
     m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
     m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
 
+    crc_state_reg[0] <= crc_state_next[0];
+    crc_state_reg[1] <= crc_state_next[1];
+    crc_state_reg[2] <= crc_state_next[2];
+
+    if (update_crc) begin
+        crc_state_reg[3] <= crc_state_next[3];
+    end
+
     if (reset_crc) begin
-        crc_state <= 32'hFFFFFFFF;
-    end else if (update_crc) begin
-        crc_state <= crc_next[3];
+        crc_state_reg[3] <= 32'hFFFFFFFF;
     end
 
     xgmii_txd_reg <= xgmii_txd_next;

diff --git a/fpga/lib/eth/rtl/axis_xgmii_tx_64.v b/fpga/lib/eth/rtl/axis_xgmii_tx_64.v
@@ -160,9 +160,8 @@ reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
 reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
 reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next;
 
-reg [31:0] crc_state = 32'hFFFFFFFF;
-
-wire [31:0] crc_next[7:0];
+reg [31:0] crc_state_reg[7:0];
+wire [31:0] crc_state_next[7:0];
 
 reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next;
 reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next;
@@ -197,9 +196,9 @@ generate
         )
         eth_crc (
             .data_in(s_tdata_reg[0 +: 8*(n+1)]),
-            .state_in(crc_state),
+            .state_in(crc_state_reg[7]),
             .data_out(),
-            .state_out(crc_next[n])
+            .state_out(crc_state_next[n])
         );
     end
 
@@ -233,57 +232,57 @@ end
 always @* begin
     casez (s_empty_reg)
         3'd7: begin
-            fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_next[0][31:0], s_tdata_reg[7:0]};
+            fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_next[0][31:0], s_tdata_reg[7:0]};
             fcs_output_txd_1 = {8{XGMII_IDLE}};
             fcs_output_txc_0 = 8'b11100000;
             fcs_output_txc_1 = 8'b11111111;
             ifg_offset = 8'd3;
         end
         3'd6: begin
-            fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_next[1][31:0], s_tdata_reg[15:0]};
+            fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_state_next[1][31:0], s_tdata_reg[15:0]};
             fcs_output_txd_1 = {8{XGMII_IDLE}};
             fcs_output_txc_0 = 8'b11000000;
             fcs_output_txc_1 = 8'b11111111;
             ifg_offset = 8'd2;
         end
         3'd5: begin
-            fcs_output_txd_0 = {XGMII_TERM, ~crc_next[2][31:0], s_tdata_reg[23:0]};
+            fcs_output_txd_0 = {XGMII_TERM, ~crc_state_next[2][31:0], s_tdata_reg[23:0]};
             fcs_output_txd_1 = {8{XGMII_IDLE}};
             fcs_output_txc_0 = 8'b10000000;
             fcs_output_txc_1 = 8'b11111111;
             ifg_offset = 8'd1;
         end
         3'd4: begin
-            fcs_output_txd_0 = {~crc_next[3][31:0], s_tdata_reg[31:0]};
+            fcs_output_txd_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]};
             fcs_output_txd_1 = {{7{XGMII_IDLE}}, XGMII_TERM};
             fcs_output_txc_0 = 8'b00000000;
             fcs_output_txc_1 = 8'b11111111;
             ifg_offset = 8'd8;
         end
         3'd3: begin
-            fcs_output_txd_0 = {~crc_next[4][23:0], s_tdata_reg[39:0]};
-            fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_next[4][31:24]};
+            fcs_output_txd_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]};
+            fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[4][31:24]};
             fcs_output_txc_0 = 8'b00000000;
             fcs_output_txc_1 = 8'b11111110;
             ifg_offset = 8'd7;
         end
         3'd2: begin
-            fcs_output_txd_0 = {~crc_next[5][15:0], s_tdata_reg[47:0]};
-            fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_next[5][31:16]};
+            fcs_output_txd_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]};
+            fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[5][31:16]};
             fcs_output_txc_0 = 8'b00000000;
             fcs_output_txc_1 = 8'b11111100;
             ifg_offset = 8'd6;
         end
         3'd1: begin
-            fcs_output_txd_0 = {~crc_next[6][7:0], s_tdata_reg[55:0]};
-            fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_next[6][31:8]};
+            fcs_output_txd_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]};
+            fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[6][31:8]};
             fcs_output_txc_0 = 8'b00000000;
             fcs_output_txc_1 = 8'b11111000;
             ifg_offset = 8'd5;
         end
         3'd0: begin
             fcs_output_txd_0 = s_tdata_reg;
-            fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_next[7][31:0]};
+            fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[7][31:0]};
             fcs_output_txc_0 = 8'b00000000;
             fcs_output_txc_1 = 8'b11110000;
             ifg_offset = 8'd4;
@@ -480,6 +479,8 @@ always @* begin
             xgmii_txd_next = fcs_output_txd_0;
             xgmii_txc_next = fcs_output_txc_0;
 
+            update_crc = 1'b1;
+
             ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg;
             if (s_empty_reg <= 4) begin
                 state_next = STATE_FCS_2;
@@ -622,10 +623,20 @@ always @(posedge clk) begin
     m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next;
     m_axis_ptp_ts_borrow_reg <= m_axis_ptp_ts_borrow_next;
 
+    crc_state_reg[0] <= crc_state_next[0];
+    crc_state_reg[1] <= crc_state_next[1];
+    crc_state_reg[2] <= crc_state_next[2];
+    crc_state_reg[3] <= crc_state_next[3];
+    crc_state_reg[4] <= crc_state_next[4];
+    crc_state_reg[5] <= crc_state_next[5];
+    crc_state_reg[6] <= crc_state_next[6];
+
+    if (update_crc) begin
+        crc_state_reg[7] <= crc_state_next[7];
+    end
+
     if (reset_crc) begin
-        crc_state <= 32'hFFFFFFFF;
-    end else if (update_crc) begin
-        crc_state <= crc_next[7];
+        crc_state_reg[7] <= 32'hFFFFFFFF;
     end
 
     swap_txd <= xgmii_txd_next[63:32];

diff --git a/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v b/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v
@@ -147,6 +147,7 @@ wire [57:0] scrambler_state;
 reg [30:0] prbs31_state_reg = 31'h7fffffff;
 wire [30:0] prbs31_state;
 wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data;
+reg [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data_reg = 0;
 
 reg [6:0] rx_error_count_reg = 0;
 reg [5:0] rx_error_count_1_reg = 0;
@@ -193,9 +194,9 @@ always @* begin
     rx_error_count_2_temp = 0;
     for (i = 0; i < DATA_WIDTH+HDR_WIDTH; i = i + 1) begin
         if (i & 1) begin
-            rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data[i];
+            rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data_reg[i];
         end else begin
-            rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data[i];
+            rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data_reg[i];
         end
     end
 end
@@ -206,12 +207,19 @@ always @(posedge clk) begin
     encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
     encoded_rx_hdr_reg <= serdes_rx_hdr_int;
 
-    if (PRBS31_ENABLE && cfg_rx_prbs31_enable) begin
-        prbs31_state_reg <= prbs31_state;
+    if (PRBS31_ENABLE) begin
+        if (cfg_rx_prbs31_enable) begin
+            prbs31_state_reg <= prbs31_state;
+            prbs31_data_reg <= prbs31_data;
+        end else begin
+            prbs31_data_reg <= 0;
+        end
 
         rx_error_count_1_reg <= rx_error_count_1_temp;
         rx_error_count_2_reg <= rx_error_count_2_temp;
         rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
+    end else begin
+        rx_error_count_reg <= 0;
     end
 end